Symposium on Quality Design (ISQED2010)

Design (ISQED2010) SanJose,California,USA ... LeakageCurrentAnalysis for Intra-ChipWirelessInterconnects 49 ... Adaptive HCI-awarePowerGatingStructure...

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2010 11th International

Symposium Design

on

Quality

Electronic

(ISQED 2010)

San

Jose, California, USA

22-24 March 2010

TIB/UB Hannover 131 918 974

4

IEEE

IEEE

ISBN:

Catalog Number:

CFP10250-PRT 978-1-4244-6454-8

89

ISQED 2010 1A:

SRAM

-

Table of Contents

Manufacturability

Chair: Saraju Mohanty

Univ of North Texas; Co-Chair:

-

Valeriy

Sukharev

Mentor

-

Graphics

1 A.1: Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM

1

RandyW.Mann, Satyanand Nalam, Jiajing Wang, Benton H.Calhoun 1A.2:

-

University of Virginia

Variability Resilient Low-power 7T-SRAM Design for nano-Scaled Technologies Touqeer Azam, Binjie Cheng, David R.S. Cumming University of Glasgow

9

-

1A.3: Robust

Importance Sampling for Efficient SRAM Yield Analysis Hagiwara], Kazuya Masu -Tokyo Institute of Technology;

Takanori Date, Shiho

15 Takashi Sato

-

Kyoto

Univ"

IA. 4: An Accurate Modeling Method Utilizing Application Specific Statistical Information and Its Application to SRAM Yield Estimation Hidetoshi Matsuoka, Hiroshi Ikeda,

1B:

Mixed

Chairs: IB. 1:

Adaptive

Signal and

Yoshinori Tomita

Hiroyuki Higuchi,

-

22

Fujitsu Microelectronics Ltd

Power Control Circuits

Syed Alam, Mark Budnik

Power

Gating for Function Units in a Microprocessor Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto Shibaura Inst of Technology; Daisuke Ikebuchi, Hideharu Amano Keio Univ; Mitaro Namiki Tokyo Univ of Agriculture & Technology;

Kimiyoshi

-

Masaaki Kondo

-

The

University

1B.2: A Dual-Level Adaptive

Kyu-Nam

-

of Electro-Communications;

Hiroshi Nakamura

-

University

of

Tokyo

Voltage System for Variation Resilience Shim, Jiang Hu, Jose Silva-Martinez Texas A&M University

38

Supply

-

1B.3: A Low Power

IB. 4:

Charge-Redistribution ADC With Reduced Capacitor Array Kandala, Ramgopal Sekar, Chenglong Zhang, Haibo Wang Southern Illinois -

Mallik

Leakage

29

-

Current

Analysis

for

Ankit More and Baris Taskin

1C:

-

Intra-Chip Wireless University

44 Univ-Carbondale

Interconnects

49

Drexel

Guaranteeing Timing Performance

Chairs: James Lei, Prof.

Fujita

IC. 1: Toward Effective Utilization of

Timing Exceptions in Design Optimization UC. San Diego Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang

54



1C.2: Useful Clock Skew

Optimization Under a Multi-Corner Multi-Code Design Framework Weixiang Shen, Yici Cai, Yongqiang Lu, Qiang Zhou Tsinghua University Wei Chen Texas A&M University" Magma Design Automation Inc.; Jiang Hu

62

-

-

-

1 C.3: Clock Buffer Polarity Assignment Considering the Effect of Delay Variations Minseok Kang and Taewhan Kim Seoul National University

69

IC.4: Linear Time Calculation of State-Dependent Power Distribution Network Capacitance Shiho Hagiwara, Koh Yamanaga, Kazuya Masu Tokyo Institute of Technology;

75

-

-

RyoTakahashi

-

The

1D: Analog

University

of

Tokyo; Takashi Sato-- Kyoto University

Design For Reliability

Chairs: Srinivas

Bodapati, Payman

Zarkesh-Ha

ID. 1: Implementing Self-Testing and Self-Repairing Analog Circuits on Field Programmable Analog Array Venkata Naresh

Mudhireddy,

Saravanan

Ramamoorthy, Haibo Wang

1D.2: BSIM4-Based Lateral Diode Model for LNA

Co-Designed

81 -

Southern Illinois Univ Carbondale

with ESD Protection Circuit

87

Ming-Ta Yang, Yang Du, Charles Teng, Tony Chang, Eugene Worley, Ken Liao, You-Wen Yau and Geoffrey Yeap Qualcomm -

1D.3: Hot Carrier Effects

Yang

on

CMOS Phase-Locked

Liu and Ashok Srivastava

-

Loop Frequency Synthesizers University Baton Rouge

92

Louisiana State

Digital Fractional-N Frequency Synthesizer Architecture Acquisition and Low Spur Northeastern University and Yong-Bin Kim

1D.4: A Novel All with Fast Jun Zhao

-

xiii

99

2A:

Lithography & Manufacturing

Chairs: Fedor Pikus,

Valeriy Sukharev

2A.1: Photomasks and the Enablement of Circuit

Peter Buck, Franklin Kalk,

Craig

West

-

Design Complexity

Toppan Photomasks,

2A.2: High Performance Source Optimization using Yao Peng, Jinyu Zhang, Yan Wang, Zhiping Yu

a -

103

Inc

Gradient-Based Method Tsinghua University

in

Optical Lithography

2A.3: Yield-constrained Digital Circuit Sizing via Sequential Geometric Programming University of California, Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costas J. Spanos -

2A.4:

Assessing Chip-Level Impact of Double-Patterning Lithography University of California San Diego; Rasit Topaloglu Kwangok Jeong, Andrew Kahng

114

Berkeley 122

-

-

2B: Power Aware

108

GlobalFoundries"

Memory Design

Chairs: Dinesh Somasekhar,

Jeffrey Fan

2B.1: A2-Port 6T SRAM Bitcell Design with Multi-Port Capabilities at Reduced Area Overhead India Dept of Telecommunication; Jawar Singh, Dhiraj Pradhan University of Bristol; D.S. Aswar

131

-

-

S.P. Mohanty 2B.2:

-

University of North Texas

USA"

Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation Satyanand Nalam, Benton Calhoun University of Virginia; Vikas Chandra, Cezary Pietrzyk, Robert Aitken ARM"

139

-

-

(DDR) Flip-Flop Using C-Elements Devarapalli, Payman Zarkesh-Ha, and Steven C. Suddarth University

Srikanth V.

-

2B.3: A Robust and Low Power Dual Data Rate

147 of New Mexico

2B.4: Optimizing Power and Throughput for M-Out-Of-N Encoded Asynchronous Circuits Jun Xu, Ge Zhang, Weiwu Hu Chinese Academy of Sciences;

151

-

Ge Zhang, Weiwu Hu

-

Loogson Technology Corporation

Limited"

2D: Poster Session 1 Chairs: Kamesh

Gadepally,

Lalitha Immaneni

2D.1: Simultaneous Extraction of Effective Gate Length and Low-field Mobility in Non-uniform Devices Vivek Joshi, Dennis Sylvester University of Michigan; Kanak Agarwal, IBM Corp.

158

2D.2: Statistical Static Timing Analysis Flow for Transistor Level Macros in a Microprocessor Vivek Nandakumar, Malgorzata Marek-Sadowska University of California Santa Barbara;

163

-

-

David Newmark, Yaping Zhan

-

Advanced Micro Devices Inc

2D.3: A Framework for Patrick

2D.4: P3

Logic-Aware Layout Analysis Gibson, Ziyang Lu, Fedor Pikus, Sridhar Srinivasan

(Power-Performance-Process) Optimization

Garima Thakral, Saraju

Dhiraj

Pradhan

-

Mohanty, Dhruva University of Bristol"

Ghai

-

171 -

Mentor

Graphics Corp

of Nano-CMOS SRAM

University

using

Statistical DOE-ILP

176

of North Texas;

2D.5: A Yield

Improvement Methodology Based on Logic Redundant Repair Repairable Scan Flip-Flop Designed by Push Rule Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui, a

Michio Komoda and Nobuhiro Tsuda

-

with

Renesas

Technology Corp.

2D.6: A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang

-

191

Tsinghua University

2D.7: "Condition-based"

Dummy Fill Insertion Method Based on ECP and CMP Predictive Models Izumi Nitta, Yuji Kanazawa, Daisuke Fukuda, Toshiyuki Shibuya, Naoki Idani, Masaru Ito, Osamu Yamasaki, Norihiro Harada, Takanori Hiramoto- Fujitsu

2D.8:

184

and Modeling of a Low Voltage Triggered SCR ESD Protection Clamp with the Very Fast Transmission Line Pulse Measurement Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Young-Sang Son, Dae-Woo Kim Dongbu Hitek Co. Ltd.

198

Analysis

206

-

2D.9: On the

211

-

Design of Different Concurrent EDC Schemes for S-Box and GF(p) Jimson Mathew, Hafizur Rahaman, Dhiraj Pradhan University of Bristol; Abusaleh Jabir

-

Oxford Brookes

University; Saraju Mohanty

2D.10: Adaptive HCI-aware Power Gating Structure Kyung Ki Kim, Haiqing Nan, Ken Choi Illinois Institute of -

xiv

-

Univ of North Texas" 219

Technology

225

Sequential Logic Auburn University Agrawal

Fan

Wang

-

2D.11: Soft Error Rate Determination for Nanoscale Netwrok Inc.;

Juniper

Vishwani

-

Low-voltage, Rail-to-Rail Input/Output Stage Operational Transconductance Amplifier (OTA) with High Linearity and its Application in a Gm-C filter Farzan Rezaei and Seyed Javad Azhari Iran University of Science and Technology (IUST)

2D.12: Ultra

231

-

2D.13: A Novel Two-Dimensional Scan-Control Scheme for Test-Cost Reduction

Chia-Yi Lin and

Hung-Ming

Chen

-

237

National Chiao Tung University

2D.14: Accelerating Trace Computation in Post-Silicon Debug Johnny Kuan, Steven Wilton, Tor Aamodt University of British Columbia

244

2D.15: Structural Fault Collapsing by Superposition of BDDs for Test Generation in Digital Circuits Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman -Tallinn University of Technology

250

2D.16: A Novel Probabilistic SET Propagation Method

258

-

Sreenivas

Gangadhar

and

Spyros Tragoudas

2D.17: Formal Verification of Full-Wave Rectifier Kusum Lata and H S

Jamadagni

Southern Illinois

using

University

Carbondale

SPICE Circuit Simulation Traces

Indian Institute of Science

-

2D.18: OBT Implementation on an OTA-C

Pablo Petrashin

-

264

Bangalore 271

Band-pass Filter

Universidad Catolica de Cordoba; Gabriela Peretti, Eduardo Romero Universidad Tecnologica Nacional" -

-

2D.19: Fast Block-iterative Domain Decomposition Algorithm for IR Drop Analysis in Yu Zhong and Martin D. F. Wong University of Illinois at Urbana Champaign

Large

Power Grid

277

-

284

Approach to Behavioral Device Modeling Dragoljub (Gagi) Drmanac, Brendon Bolin,Li-C. Wang UCSB

2D.20: A Non-Parametric

-

3A:

Variability: Design, Test,

and Characterization

Chairs: Peter O'Shea, Narendra Devta-Prasanna

Jin Sun and Janet 3A.2: Is Built-in

-

Logic Redundancy Ready Synopsys Inc.

Chris Allsup

291

Sizing by Uncertainty Second Order Cone Wang The University of Arizona

3A.1: Robust Gate

299

for Prime Time?

-

3A.3: Variation-Aware

Speed Binning

John Sartori and Rakesh Kumar Ashish Pant and Puneet

Gupta

-

307

of Multi-core Processors

-

University of Illinois

at Urbana

Champaign

UCLA"

3A.4: Use of Scalable Parametric Measurement Macro to

Improve

Semiconductor Technology Characterization and Product Test Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv Joshi, Rouwaida Kanj

315 -

IBM

3A.5: Accurate Multi-Specification DPPM Estimation Using Layered Sampling Based Simulation Ender Yilmaz Arizona State University

320

-

3B:

Emerging Device and Design Technniques

Chairs: Paul

3B.1:

Scalability of

Tong,

Bao Liu

PCMO-based Resistive Switch Device in DSM Technologies Tian, Xiaobin Wang, Wenzhong Zhu Seagate Technnology LLC

Yiran Chen, Wei Hai Li

-

327

-

Polytechnic

Institute of NYU"

3B.2: A Low Power System with Adaptive Data Compression for Wireless Monitoring of Physiological Signals and its Application to Wireless Electroencephalography Georgia Institute of Technology Jeremy Tolbert, Pratik Kabali, Simeranjit Brar, Saibal Mukhopadhya

333

-

3B.3:

Modeling

and

Analysis

of lll-V

Logic

FETs for Devices and Circuits:

Sub-22nm Technology Ill-V SRAM Cell Design Saeroonter Oh, Jeongha Park, S. Simon Wong, H.-S. 3B.4: Die-level

342

Philip Wong

-

Stanford University

Leakage Power Analysis of FinFET Circuits Considering Ajay Bhoj, Niraj Jha Princeton University

Prateek Mishra,

Process Variations

3B.5: Using Time-Aware Memory Sensing to Address Resistance Drift Issue in Multi-Level Phase Change Memory Wei Xu and Tong

347

-

Zhang

-

Rensselaer Polytechnic Institute

xv

356

3C: Power and Performance Issues in Chairs: Lech Jozwiak, Rajesh Berigei 3C.1:

System-Level Design

the Power Consumption of a Chip Multiprocessor System Average Throughput Constraint University Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram

Minimizing

362

under an

-

3C.2:

Design

of Southern California

Signal Processing Systems

of Low-Power Variation Tolerant

with Adaptive Finite Word-length Configuration Yang Liu Juniper Networks; Jibang Liu, Tong Zhang

372 -

-

Rensselaer Polytechnic Institute"

3C.3: Quality-driven Methodology for Demanding Accelerator Design Eindhoven University of Technology Lech Jozwiak and Yahya Jan

380

3C.4: Thermal-Aware Job Allocation and Scheduling for Three Dimensional Chip Multiprocessor State University of New York at Binghamton Shaobo Liu, Jingyi Zhang, Qing Wu, Qinru Qiu

390

-

-

Reliability in Multicore Systems University of Michigan-Dearborn; Jian-Jia

399

3C.5: Thermal-Aware Lifetime

Shengquan Wang

-

Chen

-

ETH Zurich"

3D: Poster Session 2 Chairs: Kamesh Gadepally, Lalitha Immaneni 3D.1: A Comprehensive Model for Gate Delay under Process Variation and Different Driving and Loading Conditions Mingzhi Gao, Zuocang Ye, Yao Peng, Yan Wang, Zhiping Yu Tsinghua -

Analysis and Bounded Skew Vinayak Honkote and Baris Taskin

3D.2: Skew

-

3D.3: A MATLAB-Based

Using

Technique

Drexel

-

Cypress

for Rotary Clocking Technology

413

for Defect Level Estimation

Data Mining of Test Fallout Data

Kanad Chakraborty

Methodology University

Constraint

406

University

versus

418

Fault Coverage

Semiconductor 422

3D.4: Constraint Analysis and Debugging for Multi-Million Instance SoC Designs Long Fei, Loa Mize, Cho Moon, Bill Mullen, Sonia Singhal Synopsys Inc -

3D.5: Variation Aware Vee Kin

Wong

428

For SOC Static Timing Analysis Intel Microelectronics (M) Sdn. Bhd.

Siong Kiong Teng

-

Asymmetric Issues of FinFET Device after Hot Carrier Injection and Impact on Digital and Analog Circuits Chenyue Ma, Hao Wang, Xiufang Zhang, Frank He, Yadong He, Xing Zhang, Xinnan

3D.7: A Novel Low

Voltage

Current

Compensated High Performance

Khalil Monfaredi, Hassan Faraji Baghtash, Iran

of Science and

University

Seyed

Javad Azhari

432 Lin

-

Peking Univ

Current Mirror/NIC

437

-

3D.6:

Guard-Banding

and

Technology (IUST) 443

3D.8: Domino Gate with Modified

Voltage Keeper Jinhui Wang, Wuchen Wu, Ligang Hou Beijing University Na Gong State University of New York at Buffalo -

of

Technology;

-

3D.9:

447

Leakage Temperature Dependency Modeling in System Level Analysis Florida International University Huang Huang, Gang Quan, Jeffrey Fan -

3D.10: Process Variation Tolerant On-Chip Communication Using Receiver and Driver Reconfiguration Ethiopia Nigussie, Juha Plosila, Jouni Isoaho University of Turku

453

-

using Process Monitoring Circuits University of Massachusetts-Amherst

3D.11: Calibration of On-Chip Thermal Sensors Basab Datta and

Wayne Burleson

-

461

3D.12: New SRAM Design Using Body Bias Technique for Ultra Low Power Applications Fasrhad Moradi, Dag Wisland, Yngvar Berg, Tuan Vu Cao University of Oslo; Purdue University Hamid Mahmoodi SanFrancisco State University; Fasrhad Moradi

468

3D.13: Body Bias Driven Design Synthesis for Optimum Performance per Area Maurice Meijer and Jose Pineda de Gyvez- NXP Semiconductors

472

-

-

-

3D.14:

Methodology

to Ensure Circuit Robustness and

Exceptional Silicon Quality High Productivity

while Proliferating Designs Across Process Revisions with Nitin Srimal

-

478

intsys 483

3D.16: Low Power Clock Gates

488

Slong Kiong Teng

-

-

3D. 15: A Multilevel Multilayer Partitioning Algorithm For Three Dimensional Integrated Circuits Yu Cheng Hu, Yin Lin Chung, Mely Chen Chi Chung Yuan Christian University

Optimization

For Clock Tree Distribution

Intel Microelectronics; Dr

Norhayati Soin

-

University

of

Malaya

3D.17: An Innovative Method to Automate the Waiver of IP-Level DRC Violations John

Ferguson, Sandeep Koranne,

David Abercrombie

xvi

-

Mentor

Graphics

493

3D.18:

Post-Synthesis Sleep

Transistor Insertion for

Leakage Power Optimization

in Clock Tree Networks

499

Houman Homayoun, Shahin Golshan,

Eli

Bozorgzadeh,

Alex Veidenbaum,

Fadi Kurdahi

-

UC-lrvine

3D.19: Antenna Violation

Avoidance/Fixing for X-Clock Routing University; National Taipei University Chung-Chieh Kuo, Lin-Jeng Gu, Trong-Yen Lee Chia-Chun Tsai

-

508

Nanhua

-

of

Technology

3D.20:

Synthesis and Formal Verification of On-Chip Protocol Transducers through Decomposed Specification Masahiro Fujita, Hideo Tanida.Tasuku Nishihara, Takeshi Matsumoto University of Tokyo: Fei Gao Fujitsu, Ltd.

515

-

-

3D.21: Level Matrix

based

on

Propagation

for

Reliability Analysis of Nano-scale Circuits

Probabilistic Transfer Matrix

Hicham Ezzat and Lirida Naviner

3D.22: The

Design

of

-

524

Telecom

Ezzat

ParisTech; Hicham

a Low-Power Low-Noise Phase Lock

Abishek Mann, Amit Karalkar, Lili He, Morris Jones

-

-

Universite Francaise d'Egypte 528

Loop San Jose State

University

3D.23: Novel Low-Power 12-bit SAR ADC for RFID Tags Daniela De Venuto Politecnico di Ban; Eduard Stikvoort; David Castro, Youri Ponomarev NXP Semiconductors

532

3D.24:

538

-

-

Adaptive Task Allocation for Multiprocessor SoCs in Real-Time Energy Harvesting Systems East China Normal University; Tongquan Wei Yonghe Guo, Xiaodao Chen, Shiyan Hu Michigan Technological University" -

-

3D.25: Multi-Programming Environment for Structure Under Pads ( SUP) and Via Arrays Pattern Recognition Automated Classification System

Suraya

Mohd Yusof and Lau Meng Tee

4A: Parametric and

-

544

National Semiconductor Sdn.Bhd

Delay Test

Chairs: Srivatsa Vasudevan, Ramyanshu Datta 4A.1: Real-Time

Adaptive Hybrid BiST Solution for Very-Low-Cost ATE Production Testing Optimal DPPM Dasnurkar and Jacob A. Abraham University of Texas at Austin

of A/D Converters with

Sachin D.

562

-

4A.2: On Evaluating Speed Path Detection of Structural Tests Jing Zeng, Jing Wang, Chia-Ying Chen, Michael Mateja AMD;

570 Li-C. Wang

-

4A.3: Slack-Based

Approach

-

UC Santa Barbara

for Peak Power Reduction during Transition Fault Testing

Manu Baby and Vijay Sarathi

-

Dubai Circuit

Design

4A.4: Case Studies of

Mixed-Signal DFT Ramyanshu Datta, Mahit Warhadpande,

577

DSO 582

Dale

Heaton, S Aarthi,

Ram Jonnavithula

-

Texas Instruments Inc

4B: PDI Chairs: Lalitha Immaneni, Kamesh

Gadepally

4B.1: Efficient Hierarchical Discretization of Off-chip Power Delivery Network Geometries for 2.5D Electrical Analysis Mosin Mondal, James Pingenot, Vikram Jandhyala

-

of

University

4B.2: Yield

Improvement of 3D ICs in the Presence of Defects in Through Signal Vias Rajeev Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske -Portland State University

5A: Advances in Power Chairs: 5A.1: A

Shiyan Hu,

590

Washington

Distribution, Placement

and

598

Routing

Vamsi Srikantham

Negotiated Congestion-based Router for Simultaneous Escape Routing Ma, Tan Yan, Martin D. F. Wong University of Illinois at Urbana-Champaign

606

-

Qiang

5A.2: Dynamic Voltage (IR) Drop Analysis and Design Closure: Issues and Challenges Nithin S K, Gowryshankar Shanmugham, Sreeram Chandrashekhar-Texas Instruments

611

5A.3:

618

Analog Placement and Global Routing Considering Wiring Symmetry Yu-Ming Yang and Iris Hui-Ru Jiang National Chiao Tung University -

5A.4: Worst-Case Noise Prediction With Non-zero Current Transition Times for

Early Power Distribution System Verification Peng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan, Chung-Kuan Cheng University of California San Diego; Xiaoming Chen Qualcomm Inc.; A. Ege Engin San Diego State University

624

-

-

-

-

-

xvii

632 -

5A.5: Fixed Outline Multi-Bend Bus Driven Floorplanning Wenxu Sheng, Sheqin Dong Tsinghua University, Yuliang Wu Satoshi Goto Waseda University"

The Chinese University of HongKong;

5B:

&

Aging Analysis

Mitigation

Chairs: Srinivas Bodapati, Keith Bowman 5B.1: Scalable Methods for the

Jianxin Fang and Sachin

Analysis and Optimization

Sapatnekar- University

of Gate Oxide Breakdown

5B.2: Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration Osaka Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye -

5B.3: Multi-Corner,

Energy-Delay Optimized,

-

652

Flip-Flop Design University of Southern California

Signal Probability Control for Relieving NBTI in SRAM Cells Kyushu University; Toshinori Sato Yuji Kunitake, Hiroto Yasuura

660 -

-

5B.5:

646

University

NBTI-Aware

Hamed Abrishami, Safar Hatami, Massoud Pedram 5B.4:

638

of Minnesota

Fukuoka

University

Early-Stage Determination of Current-Density Criticality in Interconnects Dresden University of Technology Robert Bosch GmbH; Jens Lienig Goeran Jerke

667

-

-

5C:

Test, Quality, Cost and Debug

Chairs: Priyadarsan Patra, Shankar Hemmady 5C.1: Automated Silicon Debug Data Analysis for

Techniques

Hardware Data

Acquisition Environment Yu-Shen Yang, Brian Keng, Andreas Veneris University of Toronto; Vennsa Technologies Inc. Nicola Nicolici McMaster University; Sean Safarpour a

675

-

-

5C.2:

-

Layout-Aware Illinois Scan Design for High Fault Coverage University of Bristol; Shibaji Banerjee, Jimson Mathew, Dhiraj Pradhan Saraju P Mohanty Univ of North Texas Denton

683

-

-

5C.3:

-

Smoother for Low Power Consumption in Single and Multiple Scan-Chains BIST Birzeit University; Steven F. Quigley -The University of Birmingham

Multi-Degree

Abdallatif S. Abu-lssa

689

-

5C.4: Multiplexed Trace Signal Selection Using Non-Trivial Implication-Based Correlation Sandesh Prabhakar and Michael Hsiao Virginia Tech

697

5C.5:

705

-

Modeling and Verification of Industrial Flash Memories Sandip Ray University of Texas at Austin; Jayanta Bhadra, Thomas Portlock, Ronald Syzdek Freescale Semiconductor Inc. -

-

5D:

System-level NoC,

SoC and ASIC

design

Chairs: Makram Mansour, Sao-Jie Chen 5D.1: Auto-BET-AMS: An Automated Device and Circuit Optimization Platform to Benchmark Emerging Technologies for Performance and Variability using an Analog and Mixed-Signal Design Framework

713

Angada B. Sachid, Rajesh A. Thakker, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, Mahesh B. Patil- Indian Institute of Technology Bombay; Chaitanya Sathe University of Illinois Urbana-Champaign -

5D.2: UC-PHOTON: A Novel

Photonic

Hybrid

Shirish Bahirat and Sudeep Pasricha

-

University

-

Fort Collins

5D.3: Hellfire: A Design Framework for Critical Embedded Systems' Applications Alexandra Aguiar, Sergio Johann Filho, Felipe Magalhaes, Thiago Casagrande, Fabiano Hessel

Meyer,

Adam

Improvement in NoC-based MPSoCs Hartman, Don Thomas Carnegie Mellon University

optimization in MPSoC Task Scheduling under Process Variation Momtazpour, Esmaeel Sanaei, Maziar Goudarzi Sharif University of Technology

5D.5: Power-Yield Mahmoud

6A:

730 -

PUCRS 738

-

5D.4: Slack Allocation for Yield Brett

721

Network-on-Chip for Multiple Use-Case Applications

Colorado State

747

-

Clocking Strategy for Modern Low Power Multi-Core & Structured ASICs

Chairs: Sanghamitra Roy, Mark Young 6A.1: A Revisit to the Primal-Dual Based Clock Skew Min Ni

-

Synopsys Inc.; Seda Ogrenci Memik

-

Scheduling Algorithm

755

Northwestern University"

6A.2: Clock Buffer Polarity Assignment Considering Capacitive Load Jianchao Lu and Baris Taskin Drexel University

765

6A.3: A Low Power Clock Network Placement Framework

771

-

Dawei Liu.

Qiang Zhou, Yongqiang

Lv, Jinian Bian -Tsinghua University

xviii

6A.4: Clock Routing for Structured ASICs with Via-Configurable Fabrics Yuan Ze University Rung-Bin Lin, l-Wei Lee, Wen-Hao Chen

777

-

of Power

Analysis

Supply Induced

Derek Chan and Matthew Guthaus

6B:

De-skewed Multi-Core

Actively

785

Systems

UC Santa Cruz

Modeling and Analysis of Temperature and Power

Chairs: Murat Becer, Zhuo

6B.1: Analyzing and

Power of Power-Gated Circuits

Abhishek Sinkar and Nam

Processing

Feng

Effects of Temperature Variation and NBTI

Minimizing

Leakage

on Active

6B.2: Signal

Jitter in

-

6A.5:

Sung

Kim

791

University of Wisconsin-Madison

-

Methods and Hardware-Structure

for On-line Characterization of Thermal Gradients in

Minki Cho and Saibal

Mukhopadhyay

-

Many-Core Processors Georgia Institute of Technology

797

6B.3: A Convex

Optimization Framework for Leakage-Aware Thermal Provisioning in 3D Multicore Architectures Utah State University Sanghamitra Roy and Koushik Chakraborty -

804

6B.4:

Improving

the Process Variation

Tolerability

Eun Ju Hwang, Wook Kim, Young Hwan Kim

-

of

Flip-Flops for UDSM Circuit Design of Science and Technology

812

Pohang University

818

6B.5: Interconnect Jun-Kuei

Delay and Slew Metrics Using the Extreme Value Distribution Zeng and Chung-Ping Chen National Taiwan University -

6C: Fault Tolerant

Design

Chairs: Keith Bowman, Riaz Naseer 824

6C.1: Design Methodology of Variable Latency Adders with Multistage Function Speculation Yongpan Liu, Yinan Sun, Yihao Zhu, Huazhong Yang Tsinghua University -

6C.2: Accurate Statistical Soft Error Rate

Using

(SSER) Analysis

A Quasi-Monte Carlo Framework With

Yu-Shin

Kuo, Huan-Kai Peng,

6C.3: Measurement Circuits for

Quality

Charles H.-P. Wen

Acquirinng

-

Cell Models.....

SET Pulse Width Distribution

with Sub-F01-inverter-delay Resolution Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye 6C.4:

831

National Chiao Tung University 839 -

Osaka

University

Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture: A Case Study Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sebastien Pillement University of -

6C.5:

Comparative Analysis and Study of Metastability on High-Performance Flip-Flops David Li, Pierce Chuang, Manoj Sachdev University of Waterloo

845 Rennes

853

-

6D:

Quality System-Level Design

Chairs; Anand

Iyer,

He Qian

6D.1: Reliability Analysis of Analog Circuits by Lifetime Yield Prediction Using Worst-Case Distance Degradation Rate Xin Pan and Helmut Graeb

-

861

Technische Universitaet Muenchen

6D.2: The

Compatibility Analysis of Thread Migration and Dongkeun Oh, Nam Sung Kim, Yu Hen Hu University Charlie Chung Ping Chen National Taiwan University -

DVFS in Multi-Core Processor

866

of Wisconsin-Madison;

-

6D.3:

Behavioral Modeling Flow using Statistical Learning Method Hui Li, Makram Mansour, Sury Maturi National Semiconductor; Li Wang University of California-Santa Barbara"

872

Coprocessor Design Space Exploration Using High Level Synthesis Avinash Lakshminarayana, Sumit Ahuja, Sandeep Shukla Virginia Tech

879

Methodology From Chaos in iC Implementation Kwangok Jeong and Andrew Kahng University of California San Diego

885

Analog

-

-

6D.4:

-

6D.5:

-

xix