SuperB XIV LNF IFR DAQ.ppt

SuperB IFR electronics: update on prototype electronics and IFR_DAQ

XIV SuperB Meeting - LNF

Sept-29-2010

A.Cotta Ramusino, INFN Ferrara

1

Overview

•

update on the development of the IFR prototype electronics and DAQ system


Sept-29-2010


2

SuperB IFR electronics : update on prototype electronics and DAQ

One additional (with respect to the baseline) detector layer will be read out

Second ABCD crate added

SuperB S p B IFR p prototype: t t p : • 5 layers of x-y scintillators, 1 cm thick, read in binary mode • 4 layers of scintillators 2 cm thick, read in timing mode SuperB-IFR prototype readout electronics (baseline): • “IFR_ABCD”: sensor Amplification, Bias-conditioning, Comparators, Data processing:

it samples the level of the comparators outputs @ >= 80MHz and stores it, pending the trigger request • “CAEN_TDC”: “CAEN TDC” a multi-hit lti hit TDC design d i based b d on CERN HP-TDC; HP TDC h hosted t d in i a VME crate t and d read d outt via i a VME CPU or via a VME-PCI bridge to the DAQ PC • “IFR_FE_BiRO”: collects data from IFR_ABCD cards upon trigger request and sends it to DAQ PC (via GbE) IFR_TLU TLU”:: a module (Trigger Logic Unit) to generate a fixed latency trigger based on primitives from the IFR • “IFR prototype itself or from external sources

IFR_FE_BiRO + IFR_TLU are now a single module


Sept-29-2010


3

SuperB IFR electronics : update on prototype electronics and DAQ SiPM carrier PCB

SiPM carrier PCB with NiAu plating for bonding: fits all three type of sensors being manufactured by FBK-Trento. Sensor die gluing position is determined by a countermask.

Status: • all parts needed have been delivered • SiPM bonding is ongoing at INFN-Perugia thanks to Dr Dr. Giovanni Ambrosi and Dr. Maria Ionica • bonded SiPM already delivered to INFN-Ferrara are being characterized


Sept-29-2010


4

SuperB IFR electronics : update on prototype electronics and DAQ “IFR_ABCD” card features: • ampli: two stage w/discrete components: BGA2748 + BGA2716 • discri: ADCMP563BRQ (ECL out, dual)

32 x

32 x ampli

32 x

64 x comparator w/ programmable threshold w/ fixed pulse width w/ diff ECL outputs p

64 x

SiPM

Bias Threshold DAC DAC iinside id the prototype “pizza box”

CycloneIII FPGA based daughter card Outline of the “IFR_ABCD” card A.C.R. 2009-10-06

(Amplifier, Bias, Comparator,DataProcessing)

CON NNECTOR TO T THE “LST_FE “ CRATE BACK KPLANE

2 x 32 output needed for Programmable timing mode readout only bias voltage g 32 x 32 x

4 x KEL L connector

dimensions: VME 6U x 220mm

For the readout in timing mode of the SuperB IFR prototype it is foreseen to use two comparators at different thresholds (2.5 pe and 1.5 pe for instance) for each sensor signal connector compatible with BaBar IFR signal cables bl ((re-usable): bl ) KEL 8831E-034-170LD 8831E 034 170LD • DAC: LTC2625CGN#PBF (I2C, 12bit, octal) • FPGA: Cyclone III ALTERA EP3C25Q240C8

“IFR_ABCD” needed for prototype readout : 1 for each of 4 BiR0 planes (readout at only one end of scintillator) + 1 for each of 4 planes read with TDCs (readout at both ends of scintillator)

TOTAL “IFR_ABCD” cards: 8

TOTAL “IFR IFR_ABCD ABCD” cards produced: 12 (to enable the reading of a 9th prototype layer + spares)

IFR_ABCD card: MMIC ampli design & test, schematics, and layout pre-placement by R. Malaguti, INFN-Ferrara


Sept-29-2010


5

SuperB IFR electronics : update on prototype electronics and DAQ 16 pairs x 4 P-ECL outputs to the TDCs DCs 32 x monitor outputs (analog) from the amplifiers (on MMCX connectors)

96 pin DIN connector to the backplane

Detail of the digital “IFR IFR_ABCD ABCD” daughter card 32 x SiPM inputs (on MMCX connectors)

“IFR_ABCD” status update :

“IFR_ABCD” card


• 8 boards delivered and tested • 4 boards expected in TWO WEEKS

Sept-29-2010


6


translators

TRIGGER PORT

A.C.R. 2010-03-17

Flat cable

HSMC breakout adapter

Power TO

Signal level

add-on card

“IFR_FE_BiRO_TLU_carrier”

DIN connectoors to the LST_FE cratee backplane

“IFR_FE_BiRO_TLU” module features (new): The functions of the IFR_FE_BiRO and of the IFR_FE_TLU cards are combined into a single system made of

• a carr carrier er card wh which ch f fits ts in n the “LST LS _FE FE”

crate (6U x 220mm depth) • an add-on card : it’s simply the ALTERA Cyclone III development kit (DK-DEV3C120N) equipped with breakout adapters for the kit’s HSMC connectors

The carrier card hosts level adaptors and application specific I/O ports which allow the add-on card to: Flat cable •receive receive power HSMC breakout adapter •receive the “fast OR” signals from the “ABCD” cards to generate triggers from •generate and distribute triggers (also to the TDC system) y ) •generate and distribute clock and reset signals A second (also to the TDC system) IFR_FE_BiRO_TLU •poll data from the “ABCD” cards is needed since the •configure g the programmable p g resources on the introduction of a “ABCD” cards 2nd crate •connect to the host PC running the DAQ software via ethernet (tcp/ip)

Outline of the “IFR_FE_BiRO_TLU” module XIV SuperB Meeting - LNF

Sept-29-2010

Total “IFR_FE_BiRO_TLU” needed for the prototype readout: 1 A.Cotta Ramusino, INFN Ferrara

7


translators

TRIGGER PORT

A.C.R. 2010-03-17

Flat cable

Flat cable

Power T TO

Signal level

add-on c card

“IFR_FE_BiRO_TLU_carrier”

DIN connnectors to thhe LST_FE E crate backplaane

“IFR_FE_BiRO_TLU” module features: (continues)

HSMC breakout adapter p

The FPGA on board the add-on card is connected to the RUN CONTROL/DAQ PC of the prototype test setup via an Ethernet port. The FPGA features a NIOS-II NIOS II microcontroller which implements the full TCP/IP stack. The NIOS-II receives commands (i.e. START, STOP, INIT) from the RUN CONTROL/DAQ PC on a TCP server socket and sends data to a TCP server socket on the PC. Data is collected through the LST_FE backplane from the “ABCD” cards upon a trigger request. The data collection section of the FPGA is coded in VHDL.

The FPGA of the add-on card generates the timing (clock and reset) for all the digitizers and handles the trigger distribution as well.

Outline of the “IFR_FE_BiRO_TLU” module XIV SuperB Meeting - LNF

Sept-29-2010


8


“IFR_FE_BiRO_TLU” interface status update : • 2 carrier boards have been delivered • 2 assemblies have been tested and are being used to test the Binary Mode readout (“BiRO”) crates One more interface card will have to be stuffed to be kept as a spare

Th “IFR_FE_BiRO_TLU The IFR FE BiRO TLU” module d l


Sept-29-2010


9


“IFR_FE_BiRO” crate status update: A notebook PC is presently used to control the IFR_FE_BiRO_TLU board via Ethernet using standard TCP/IP socket programming. The IFR_FE_BiRO_TLU has access to the IFR_ABCD cards to configure them and read them out In the current test setup the IFR_ABCD cards are programmed to use their internal t t pulse test l generators. t The “FAST_OR” outputs of the IFR_ABCD cards y the IFR_FE_BiRO_TLU _ _ _ are received by which generates a trigger and reads out the boards through the crate’s backplane. The “IFR_FE_BiRO” CRATE


Sept-29-2010


10

SuperB IFR electronics : update on prototype electronics and DAQ DATA COLLECTOR task on the host PC

Debug console for the NIOS-II microcontroller on board the IFR_FE_BiRO_TLU. The NIOS-II executes 2 tasks: a “simple socket server” connected to the run control task on the host PC and the “event transmission” which sends data to the host PC

RUN CONTROL task on the host PC A il bl commands Available d are, up tto now: •BiRO_TLU_config •ABCD_init •ABCD_ratemeter •RUN_start •RUN_stop _ p

Internal pulser test results: screenshots from the notebook used to control and collect data from the IFR_FE_BiRO crate 11 XIV SuperB Meeting - LNF Sept-29-2010 A.Cotta Ramusino, INFN Ferrara


Segnali di lettura per le schede ABCD

Scrittura dei dati dell’evento nella memoria di pacchetto della porta TCP/IP

Il flag “datavalid” segnala al NIOS-II della BiRO-DAQ che il pacchetto da 1 evento e’ pronto e puo’ quindi chiamare la send()


SuperB IFR electronics : update on prototype electronics and DAQ Record from the SuperB_data.txt where the DATA COLLECTOR task stores the events t


SuperB IFR electronics : update on prototype electronics and DAQ “TDC subsystem” features: The TDC subsystem uses 2 commercial TDC modules based on CERN’s HP-TDC to digitze the time of arrival of the pulses from the “ABCD” boards. The TDC subsystem will also use a VME-based module to interface to the “IFR_FE_BiRO_TLU”

VME –b based TLU in nterface

HP-TDC C based Timee digitizer

HP-TDC based Timee digitizer

PCI-VM ME bridge

“TDC TDC subsystem” subsystem VME crate

and receive trigger/timing signals

The TDC subsystem VME crate will be controlled and read out by the “TDC-PC” via a PCI-VME bridge. The TDC_PC will then send the triggered data to the RUN CONTROL/DAQ PC via a TCP/IP connection. to IFR_FE_BiRO_TLU IFR FE BiRO TLU to RUN CONTROL/DAQ PC


Sept-29-2010


14


VME –b based TLU in nterface

HP-TDC C based Timee digitizer

HP-TDC based Timee digitizer

PCI-VM ME bridge

“TDC TDC subsystem” subsystem VME crate

to IFR_FE_BiRO_TLU IFR FE BiRO TLU to RUN CONTROL/DAQ PC

“TDC subsystem” status update : • TDC readout: DONE • port toward the Online Detector Control program : DONE, • acknowledgments to Stefano Chiozzi, INFNFerrara and Nicola Dalpasso, above, undergraduate student at the Ferrara University


Sept-29-2010


15



Sept-29-2010


16



Sept-29-2010


17



Sept-29-2010


18



Sept-29-2010


19



Sept-29-2010


20



Sept-29-2010


21

SuperB XIV LNF IFR DAQ.ppt

Recommend Documents