Modular Multilevel Converters for HVDC power stations

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Modular Multilevel Converters for HVDC power stations Nicola Serbia

To cite this version: Nicola Serbia. Modular Multilevel Converters for HVDC power stations. Engineering Sciences [physics]. Institut National Polytechnique de Toulouse - INPT, 2014. English.

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%JSFDUFVS T EFʾÒTF M. LADOUX, Philippe M. MARINO, Pompeo Jury : LADOUX, Philippe (Directeur de Thèse) MARINO, Pompeo (Directeur de Thèse) DEL PIZZO, Andrea (Rapporteur) MACHMOUM, Mohamed (Rapporteur) EGROT, Philippe (Examinateur) IMPROTA, Vinvenzo (Examinateur)



MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

Acknowledgements The Phd thesis is not just an intensive work period of three years. This is an experience of life where I had the opportunity to increase my personal and professional experience. In these three years through the interfacing with persons that assisted me and with which I had the honor to share this period. With them (directly and un-directly), I had the opportunity to grow up my professional knowledge and to improve my personality. Firstly I would like to thanks the members of the jury: Mr. Mohamed MACHMOUM, Professor at the Polytech Nantes and Mr. Andrea DEL PIZZO, Professor at the Università degli Studi di Napoli Federico II, for having read in details this dissertation and for having wrote a very detailed and exhaustive report about the manuscript as examiners of my thesis by contributing to the improvement of the work. Mr. Philippe EGROT, engineer at EDF in the HVDC frame for having accepted to review my thesis and having been part of the jury. Mr. Vincenzo IMPROTA, Engineer at Ansaldobreda SpA for having accepted to review my thesis and having been part of the jury. Then I would like to thanks Mr. Paolo BORDIGNON, executive vice president of Rongxin Power Electronic Co., Ltd for his economic (by means the company) and professional support to the development of the work Then I like to say thank you to my two supervisors. Peoples that I'll never stop thanking. I can consider these two persons the only guys who attended to my professional development and they principally contributed to my professional and recently personal maturation. I know that is very difficult to meet persons like them. These two persons are alphabetically sorted below. Thank you to Mr. Philippe LADOUX, Professor at the Institut National Polytechnique of Toulouse and director of my thesis. Firstly for having accepted me as Ph.D. student and to have believed that for me was possible facing this much hard and tricky subject. Thank for giving me his support and his methods, and for best having supervised my studies. He taught me how the complex world of engineering can become very easy and pleasurable. For me was an honor working with him and I hope that a new working adventure is going to start. Besides the professional aspect I found a person with a great humanity and friendship. It was able to make easy all the difficulties that I had at my arriving in France. Thank you, Philippe his family, because they spent a lot of time with me giving me the honor to meet me at their home. With their help I never had any difficulties. Thank you for their precious friendship.

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Nicola Serbia Thank you to Mr. Pompeo MARINO, Professor at the Seconda Università degli Studi di Napoli, supervisor of my final project of the “Laurea” degree in 2007, supervisor of my final project of the “Laurea Magistrale” degree in 2010 and finally my PhD thesis director. Thank you for trusting in me. Thank you having gave me the opportunity. Thank for your very precious suggestions and your intuitions. He taught me that everything is possible by working hard and fine. Under the human aspect I think that there are many things to learn by him. He made my Ph.D. period a superlative experience. He shared with me his passion for the sailing which for me was a very formative and fantastic experience. So, of course I’m sure that a very great friendship has been consolidated. It is always an honor spending time with him, thank you Prof.! Thanks to the LAPLACE, I have met a lot of people, and I have to say thanks to someone of them: All the members of the group Convertisseur Statique, expecially the responsible Mr. Frédéric RICHARDEAU. Thank you “Les Super Filles”! Carine BASTIE, Lea BOULANGER, Cécile DAGUILLANES, Catherine MOLL-MAZELLA and Valérie SCHWARZ. Besides their impeccable professionalism they made the time at the laboratory more pleasant and cheerful (particularly the Valerie’ sneezes). Mr Jean-Marc BLAQUIERE for his great technical experience and for having helped me in the realization of the prototype. Mr Jeaques BENAIOUN for his great technical informatics experience. He was very efficient to solve my informatics problem. All the PhD students, Post-Doc and others that shared all the good times, especially: Andre DE ANDRADE (dedé), he helped me especially at the beginning. Thank for your friendship. He never left me alone and Julio BRANDELERO, Clement NADAL and Damien BIDART, les “colocataires plus emportants ». François PIGACHE, a very good friend always helpful and friendly. Then Johannes SCHELLER and Samer YAMMINE, I found very good friends; they are principally responsible of my “intensive week-ends”. Alberto ROSSI, Etienne FOURNIER (thank you for your help for the language), Julie EGALON, Sebastien SANCHEZ (mon “professeur de toulousian”), Maud TAUZIA (ma prof de Français) Amanda VELAZQUEZ SALAZAR (“la nina”), Mustapha DEBBOU, Bernardo COUGO, Eduard Hernando SOLANO SAENZ, Julian Andres SUAREZ, Benedikt BYRNE sorry if I’ve forgotten someone.

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Then I say thank you to Giuliano RAIMONDO, thank to his help especially at the beginning. It was principal responsible of my integration. Thank you for your friendship too. I have also to say thanks to the people of DITEN from the University of Genova, especially to Gianluca PARODI, Luis VACCARO and Prof. Mario MARCHESONI. I have also to say thanks to the people of the Dipartimento di Ingegneria Industriale e dell’Informazione of the Seconda Università degli Studi di Napoli, especially to:

Nicola GRELLA and Angela BRUNITTO for their efficiency in all the bulky administrative procedures. My Italians colleagues: Michele FIORETTO for his friendship and for his time spent together Luigi and Guido RUBINO, for their technical experience and their very precious help. Especially lately. Felice Andreozzi, Marco BALATO and Luigi FEOLA. Professors Roberto LANGELLA and Alfredo TESTA for having shared several time of his research with me, and all the others PhD students I’ve met in Aversa. At the end I’d like to say thank you to my FAMILY, they supported always my choices. They are responsible of my ambition. Thank you for having always believed in me and for me is an honor being your son. I hope and I know that this my new goal helps your happiness. Then at the end there is ROSSELLA, despite the distance she is able to make me a happy man again. Moreover she makes me want be a better man.

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SUMMARY This work was performed in the frame of collaboration between the Laboratory on Plasma and Energy Conversion (LAPLACE), University of Toulouse, and the Second University of Naples (SUN). This work was supported by Rongxin Power Electronic Company (China) and concerns the use of multilevel converters in High Voltage Direct Current (HVDC) transmission. For more than one hundred years, the generation, the transmission, distribution and uses of electrical energy were principally based on AC systems. HVDC systems were considered some 50 years ago for technical and economic reasons. Nowadays, it is well known that HVDC is more convenient than AC for overhead transmission lines from 800 - 1000 km long. This break-even distance decreases up to 50 km for underground or submarine cables. Over the twenty-first century, HVDC transmissions will be a key point in green electric energy development. Due to the limitation in current capability of semiconductors and electrical cables, high power applications require high voltage converters. Thanks to the development of high voltage semiconductor devices, it is now possible to achieve high power converters for AC/DC conversion in the GW power range. For several years, multilevel voltage source converters allow working at high voltage level and draw a quasi-sinusoidal voltage waveform. Classical multilevel topologies such as NPC and Flying Capacitor VSIs were introduced twenty years ago and are nowadays widely used in Medium Power applications such as traction drives. In the scope of High Voltage AC/DC converters, the Modular Multilevel Converter (MMC), proposed ten years ago by Professor R. Marquardt from the University of Munich (Germany), appeared particularly interesting for HVDC transmissions. On the base of the MMC principle, this thesis considers different topologies of elementary cells which make the High Voltage AC/DC converter more flexible and easy suitable respect to different voltage and current levels. The document is organized as follow. Firstly, HVDC power systems are introduced. Conventional configurations of Current Source Converters (CSCs) and Voltage Source Converters (VSCs) are shown. The most attractive topologies for VSC-HVDC systems are analyzed. The operating principle of the MMC is presented and the sizing of reactive devices is developed by considering an open loop and a closed loop control. Different topologies of elementary cells offer various properties in current or voltage reversibility on the DC side. To compare the different topologies, an analytical approach on the power losses evaluation is achieved which made the calculation very fast and direct. A HVDC link to connect an off-shore wind farm platform is considered as a case study. The nominal power level is 100 MW with a DC voltage of 160 kV. The MMC is rated considering press-packed IGBT and IGCT devices. Simulations validate the calculations and

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also allow analyzing fault conditions. The study is carried out by considering a classical PWM control with an interleaving of the cells. In order to validate calculation and the simulation results, a 10kW three-phase prototype was built. It includes 18 commutation cells and its control system is based on a DSP-FGPA platform.

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RESUME Les travaux présentés dans ce mémoire ont été réalisés dans le cadre d’une collaboration entre le LAboratoire PLAsma et Conversion d’Énergie (LAPLACE), Université de Toulouse, et la Seconde Université de Naples (SUN). Ce travail a reçu le soutien de la société Rongxin Power Electronics (Chine) et traite de l’utilisation des convertisseurs multi-niveaux pour le transport d’énergie électrique en courant continu Haute Tension (HVDC). Depuis plus d’un siècle, la génération, la transmission, la distribution et l’utilisation de l’énergie électrique sont principalement basées sur des systèmes alternatifs. Les systèmes HVDC ont été envisagés pour des raisons techniques et économiques dès les années 60. Aujourd’hui il est unanimement reconnu que ces systèmes de transport d’électricité sont plus appropriés pour les lignes aériennes au-delà de 800 km de long. Cette distance limite de rentabilité diminue à 50 km pour les liaisons enterrées ou sous-marines. Les liaisons HVDC constituent un élément clé du développement de l’énergie électrique verte pour le XXIème siècle. En raison des limitations en courant des semi-conducteurs et des câbles électriques, les applications à forte puissance nécessitent l’utilisation de convertisseurs haute tension (jusqu’à 500 kV). Grâce au développement de composants semi-conducteurs haute tension et aux architectures multicellulaires, il est désormais possible de réaliser des convertisseurs AC/DC d’une puissance allant jusqu’au GW. Les convertisseurs multi-niveaux permettent de travailler en haute tension tout en délivrant une tension quasi-sinusoïdale. Les topologies multi-niveaux classiques de type NPC ou « Flying Capacitor » ont été introduites dans les années 1990 et sont aujourd’hui couramment utilisées dans les applications de moyenne puissance comme les systèmes de traction. Dans le domaine des convertisseurs AC/DC haute tension, la topologie MMC (Modular Multilevel Converter), proposée par le professeur R. Marquardt (Université de Munich, Allemagne) il y a dix ans, semble particulièrement intéressante pour les liaisons HVDC. Sur le principe d’une architecture de type MMC, le travail de cette thèse propose différentes topologies de blocs élémentaires permettant de rendre le convertisseur AC/DC haute tension plus flexible du point de vue des réversibilités en courant et en tension. Ce document est organisé de la manière suivante. Les systèmes HVDC actuellement utilisés sont tout d’abord présentés. Les configurations conventionnelles des convertisseurs de type onduleur de tension (VSCs) ou de type onduleur de courant (CSCs) sont introduites et les topologies pour les systèmes VSC sont ensuite plus particulièrement analysées. Le principe de fonctionnement de la topologie MMC est ensuite présenté et le dimensionnement des éléments réactifs est développé en considérant une commande en boucle ouverte puis une commande en boucle fermée. Plusieurs topologies de cellules élémentaires sont proposées afin d’offrir différentes possibilités de réversibilité du courant ou de la tension du côté continu. Afin de comparer ces structures, une approche analytique de

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l’estimation des pertes est développée. Elle permet de réaliser un calcul rapide et direct du rendement du système. Une étude de cas est réalisée en considérant la connexion HVDC d’une plateforme éolienne off-shore. La puissance nominale du système étudié est de 100 MW avec une tension de bus continu égale à 160 kV. Les différentes topologies MMC sont évaluées en utilisant des IGBT ou des IGCT en boitier pressé. Les simulations réalisées valident l’approche analytique faite précédemment et permettent également d’analyser les modes de défaillance. L’étude est menée dans le cas d’une commande MLI classique avec entrelacement des porteuses. Enfin, un prototype triphasé de 10kW est mis en place afin de valider les résultats obtenus par simulation. Le système expérimental comporte 18 cellules de commutations et utilise une plate-forme DSP-FPGA pour l’implantation des algorithmes de commande.

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RIASSUNTO Durante i tre anni del corso di Dottorato di Ricerca in Conversione dell’Energia, l’attività si è sviluppata nel quadro di una collaborazione tra la Seconda Università degli Studi di Napoli, il laboratorio LAPLACE (Laboratoire Plasma et Conversion d'Energie) dell’Università di Toulouse. Il lavoro di tesi è stato inoltre supportato dalla Rongxin Power Electronic (Cina) e concerne l’impiego del convertitore multilivello per le trasmissioni in corrente continua ad alta tensione comunemente conosciute in letteratura come High Voltage Direct Currents (HVDC). Nell’ultimo secolo, la generazione, la trasmissione, la distribuzione ed il consumo di energia è stato principalmente basato su sistemi in corrente alternata (AC). I sistemi di tipo HVDC si sono resi attrattivi negli ultimi 50 anni per una serie di ragioni di natura tecnica ed economica. Oggi, è ben noto che le connessioni HVDC sono più convenienti rispetto a quelle AC per distanze superiori a linee comprese tra 800 – 1000 km. Questa distanza di soglia si riduce quando si parla di trasmissioni sottomarine. Nel ventunesimo secolo, le trasmissioni HVDC saranno un punto chiave anche per lo sviluppo e l’integrazione con il preesistente sistema elettrico delle energie rinnovabili. A causa della limitazione in corrente dei dispositivi semiconduttori e dei cavi di trasmissione, l’impiego di alte potenze si traduce nell’impiego di convertitori ad alte tensioni. Grazie alo sviluppo di dispositivi semiconduttori, è oggi possibile ottenere conversioni AC/DC per alte potenze dell’ordine dei GW. Per diversi anni, i convertitori Multilivello di tipo sorgente di tensione, in letteratura noti come voltage source converters (VSC), consentono di lavorare ad alti livelli di tensione e di imporre una forma d’onda di tensione al lato AC pressoché sinusoidale. Le classiche topologie come NPC e Flying Capacitors ti tipo VSI sono state introdotte circa venti anni addietro ed oggi sono generalmente utilizzate in applicazioni di media potenza come gli azionamenti delle macchine elettriche. Per la conversione AC/DC ad alta tensione, il convertitore modulare multilivello (MMC), proposto circa dieci anni fa dal professore R. Marquardt della Università di Monaco (Germania), è sembrato particolarmente attrattivo ed interessante per le trasmissioni HVDC. Partendo dalla struttura HVDC, si sono considerate all’interno del lavoro di differenti topologie di celle elementari che rendono il convertitore più flessibile e più facilmente adattabile rispetto ai differenti livelli di tensione e corrente. Il lavoro di tesi si è svolto secondo il seguente ordine: in primis, i sistemi HVDC sono stati introdotti. Le configurazioni convenzionali basate sui convertitori a sorgente di corrente (CSC) e quelle basate sui convertitori a sorgente di tensione (VSC) sono state descritte. In entrambi i casi il principio di funzionamento sul quale si basa il trasferimento di potenza è stato descritto. Parallelamente è stato effettuato uno studio sullo stato dell’arte dei semiconduttori impiegati nella elettronica di potenza e sono state tratte viii

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valutazioni sui meglio adattabili alle connessioni HVDC. Si è evinto dedotto che l’orientamento delle trasmissioni HVDC è basato sulla conversione VSC. Per tale motivo ha analizzato le topologie multilivello più attrattive. I principi di funzionamento dell’MMC sono stati studiati e il dimensionamento dei componenti reattivi è stato proposto considerando due differenti approcci a seconda del controllo ipotizzato per il sistema. Nel corso del suo studio si è inoltre evinto che differenti topologie di celle elementari offrono varie proprietà reversibilità di corrente o di tensione sul lato DC. Al fine di comparare le differenti topologie, si è proposto un nuovo approccio analitico per lo studio delle perdite ha reso il calcolo veloce e diretto. In tale ambito una nuova struttura multilivello è stata introdotta. Tale topologia è stata pensata per sistemi AC/DC basata su raddrizzatori a ponte di diodi. Tali sistemi infatti sono composti da trasformatori di rete di tipo ZigZag configurati in tal modo da compensare le componenti continue della corrente introdotte dal raddrizzatore a ponte lato AC. La topologia proposta nel lavoro di tesi è pensata per rimpiazzare i vecchi raddrizzatori obsoleti e poco versatili con una struttura multilivello capace di avere un impatto armonico ridotto ed un funzionamento a quattro quadranti in termini di potenza. In una fase successiva gli studi sono stati validati attraverso una campagna di simulazioni. Il caso considerato è quello di un sistema HVDC-VSC multiterminal chiamato ad interfacciare un parco eolico off-shore sito in Cina. La potenza del sistema è di 100 MW con una tensione DC di 160 kV. Il convertitore MMC è stato dimensionato considerando dei dispositivi IGBT di tipo press-Pack e dei dispositivi IGCT. Le simulazioni hanno validato le simulazioni anche in condizioni di fault. Lo studio del controllo per il sistema è stato effettuato in prima battuta considerando la classica modulazione PWM. Tale modulazione è stata implementata sfasando le portanti tra le celle che compongono la struttura. Al fine di validare lo studio e i risultati di simulazione, un prototipo trifase da 10 kW è stato realizzato. Tale prototipo è formato da 18 celle di commutazione di tipo semplici. Il sistema di controllo è stato implementato grazie una piattaforma basata su logica DSP-FPGA.

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RESUME DE LA THESE EN LANGUE FRANÇAISE Chapitre I : Les systèmes HVDC Ce chapitre présente les systèmes pour le transport d’énergie électrique en courant continu à haute tension (HVDC) et souligne leur rôle clé dans le développement des énergies renouvelables. Ces 40 dernières années, les systèmes HVDC ont été développés pour le transport de l’électricité compte tenu des considérations techniques et économiques suivantes : •

• •

Par rapport aux systèmes en courant alternatif, la transmission en courant continu, malgré le coût additionnel des sous-stations de conversion, est économiquement intéressante pour des distances supérieures à 800 km dans le cas des lignes aériennes et 50 km pour les lignes enterrées ou sous-marines (Figure I-1). Les systèmes en courant continu permettent les interconnexions entre des réseaux hétérogènes qui peuvent être asynchrones entre eux, et/ou à fréquences différentes. L’amélioration constante de la technologie des dispositifs semi-conducteurs a permis d’atteindre des niveaux de puissance de l’ordre du GW.

Nous illustrons la description des principes de connexion HVDC en faisant référence aux principales installations actuelles. Deux principaux types de connexion HVDC sont utilisés. Celles basées sur des convertisseurs AC/DC de type onduleur de courant (CSC) et celles basées sur des convertisseurs AC/DC de type onduleur de tension (VSC). Avant d’entrer dans les détails de fonctionnement de ces liaisons HVDC, nous décrivons les principaux dispositifs semi-conducteurs disponibles sur le marché et employés pour les applications « haute tension ». Nous donnons en particulier une description détaillée des technologies en boitier pressé (press-pack), qui peuvent être considérées comme les meilleures candidates pour la mise en œuvre de semi-conducteurs en haute tension et fort courant. Nous donnons ensuite une description des convertisseurs CSC à base de thyristors et présentons les principes de réglage de la puissance. Du fait que les thyristors ne présentent pas de problèmes de mise en série directe, les convertisseurs peuvent atteindre des tensions de l’ordre de 500 kV. Bien que simple et robuste, la topologie de type CSC ne permet pas un contrôle indépendant des puissances active et réactive et absorbe également des courants non sinusoïdaux qui nécessitent des dispositifs de filtrage occupant 20 à 30% de la superficie totale d’une sous-station (Figure I-42). Les convertisseurs de type VSC commandés en modulation de largeur d’impulsion (MLI) sont basés sur des semi-conducteurs à amorçage et blocage commandées (IGBT ou IGCT). Les topologies HVDC-VSC permettent d’effectuer le transport d’énergie en courant continu en offrant, vis-à-vis des réseaux AC, des réglages indépendants des puissances active et réactive . La mise en série directe d’IGBT étant très délicate, la tension reste aujourd’hui limitée à 320 kV pour une topologie classique à trois niveaux de tension par bras. x

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Nous décrivons ensuite des topologies multiniveaux qui sont adaptées à la haute tension. Par rapport aux structures classiques, elles peuvent garantir une forme d’onde quasi sinusoïdale en réduisant les harmoniques et en permettant une réduction des éléments de filtrage. Parmi ces topologies multiniveaux, nous présentons le principe de base du convertisseur modulaire multiniveaux (MMC) qui sera développé dans la suite de la thèse. Cette structure consiste en la mise en série de blocs élémentaires identiques (Figure I-62). Elle est aujourd’hui préférée aux structures traditionnelles car elle garantit une modularité en termes de production industrielle et n’a théoriquement pas de limite supérieure pour la valeur de la tension DC puisqu’il est toujours possible d’ajouter des blocs élémentaires en série. Chapitre II : Le convertisseur modulaire multiniveaux (MMC) Nous étudions dans ce chapitre le convertisseur AC/DC modulaire multiniveaux. Le circuit triphasé est formé de la connexion de deux bras par phase (Figure II-1). Chaque bras impose la moitié de la tension DC ainsi que la tension AC. Chacun des bras conduit également un tiers du courant DC et la moitié du courant AC. La combinaison des deux bras nous permet d’obtenir les courants et tensions AC et DC nécessaires au transfert de puissance par la liaison DC. Après une première analyse du fonctionnement, nous proposons un modèle moyen de la structure (macro modèle) afin de simplifier l’étude de dimensionnement. Ce modèle ne prend pas en considération les effets des harmoniques dus aux dispositifs de commutation mais garantit une plus grande rapidité dans les simulations, les calculs étant simplifiés. L’étude est en outre valable quelle que soit la topologie des blocs élémentaires et considère une commande MLI classique avec entrelacement des porteuses. Nous effectuons une analyse préliminaire des courants et tensions du convertisseur. Du point de vue des harmoniques de courant, outre les composantes DC et AC, chacun des bras conduit une composante au double de la fréquence fondamentale (Figure II-9). Cette composante découle de l’équilibrage énergétique entre les deux bras qui composent chaque phase. La minimisation de cette composante jouant un rôle fondamental dans le dimensionnement des éléments de filtrage, nous étudions par la suite deux possibilités liées au pilotage de la structure. Des simulations sur un système de 100 MW composé de 64 convertisseurs élémentaires par bras valident l’étude. Dans le premier cas, nous adoptons un contrôle de la structure qui ne permet pas de supprimer l’harmonique de second ordre du courant de bras. La limitation de son amplitude est alors effectuée exclusivement par les composants passifs. Ainsi, en augmentant la capacité du condensateur de chaque bloc élémentaire et l’inductance série de chaque bras, l’amplitude de cet harmonique peut être diminuée. Pour ne pas limiter la plage de réglage du convertisseur à cause des valeurs élevées de l’inductance de bras, nous proposons alors d’utiliser deux inductances couplées par phase. Elles sont couplées de manière à présenter une valeur élevée vis-à-vis de l’harmonique de courant d’ordre deux tandis qu’une valeur faible est présentée visà-vis de la composante fondamentale de courant. Cette approche requiert bien entendu une structure plus coûteuse mais un circuit de contrôle plus simple. Le second cas considère une commande plus complexe capable de contrôler chaque courant de bras de façon à obtenir la référence désirée à la fréquence fondamentale tout en xi

Nicola Serbia supprimant la composante de rang deux. Dans ces conditions, le dimensionnement des composants passifs est réduit puisque seul l’harmonique de courant à fréquence fondamentale est considéré. La complication du contrôle n’est pas aujourd’hui un problème grâce au large choix de dispositifs numériques de commande disponibles sur le marché. Ainsi, avons-nous privilégié ce cas dans la suite du travail de thèse. Chapitre III : Nouvelles topologies de convertisseurs modulaires multiniveaux. Dans ce chapitre, nous proposons et étudions et différentes topologies pour le convertisseur modulaire multiniveaux afin d’obtenir différentes propriétés en termes de réversibilité de tension ou de courant. La première topologie considérée pour réaliser un bloc élémentaire est une simple cellule de commutation. C’est celle qui est utilisée dans la version de base du MMC (Figure III-5). Cette topologie est bidirectionnelle en courant et unipolaire en tension. Pour cette raison, en cas de court-circuit sur le côté DC, le système multiniveaux n’est pas en mesure de limiter le courant ce qui risque de détruire les semi-conducteurs. Seules les cellules bipolaires sont en mesure de limiter le courant en cas de court-circuit sur le côté DC. Dans ce but, nous introduisons le pont asymétrique et le pont complet. La première structure (Figure III-8) est bipolaire en tension mais unidirectionnelle en courant. Cette topologie rend le MMC peu adaptée au réglage de la puissance réactive mais dans le cas où le facteur de puissance est unitaire, cette topologie étant unidirectionnelle en courant, le système effectue l’inversion de la puissance en inversant la tension DC, ce qui est typique des CSC à thyristors. Pour cette raison, une telle structure peut être utilisée pour le remplacement immédiat des convertisseurs à thyristors. Par la suite, nous considérons également le pont complet (Figure III-11). Assurément, cette structure est la plus flexible car elle est simultanément bidirectionnelle en courant et en tension, mais par rapport aux deux précédentes elle exige le double de composants semi-conducteurs. Dans ce chapitre, nous présentons une approche analytique pour le calcul des pertes dans les semi-conducteurs. Elle permet par la suite une évaluation directe et rapide du rendement du convertisseur AC/DC. Jusqu’à présent, dans la littérature, une telle approche n’avait pas été proposée pour le MMC car la forme d’onde du courant dans les semi-conducteurs rend le calcul des pertes très complexe. A la suite de la validation des formules analytiques par des simulations avec les modules de calcul de pertes du logiciel PSIM, nous effectuons une comparaison du rendement du système en considérant l’utilisation des trois topologies mise en avant ci-dessus. La comparaison est effectuée pour une puissance de 100 MW et une tension DC de 160 kV. En termes de rendement, la structure à simples cellules est la moins dissipative. Les deux autres à base de cellules bipolaires présentent des pertes plus élevées car elles requièrent au final plus de composants semi-conducteurs. Bien que ces topologies permettent au système de mieux gérer les conditions de court-circuit DC, une baisse même minime au niveau du rendement (de l’ordre 0,5%) est difficilement acceptable compte tenu des niveaux de puissance mis en jeu. Nous présentons ensuite une nouvelle structure modulaire multiniveaux (Figure III-28) de convertisseur AC/DC. Contrairement à la version traditionnelle, cette topologie adopte pour xii

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chaque phase une seule branche de blocs élémentaires et une seule boucle de contrôle du courant. D’autre part, celle-ci est connectée avec le réseau alternatif triphasé à travers un transformateur zig-zag. Le dimensionnement des composants réactifs et des semi-conducteurs est identique à la version de base. A titre d’exemple, nous proposons cette nouvelle structure pour remplacer les anciens redresseurs à base de diodes ou thyristors (Figure III-30). Nous développons ce remplacement en conservant le même transformateur de ligne et ainsi les mêmes niveaux de courant et tension. Nous effectuons les simulations en considérant un système de 10 MVA. Chapitre IV : Commande MLI pour les convertisseurs modulaires multiniveaux Nous développons dans ce chapitre le contrôle pour les structures MMC en considérant une modulation (commande MLI classique avec entrelacement des porteuses). A chaque fois, les simulations valident l’étude en considérant un système de 100 MW avec une tension de 160 kV sur le côté continu et côté alternatif un fonctionnement à facteur de puissance unitaire en mode onduleur ou redresseur. La commande pour convertisseurs modulaires multiniveaux proposée dans ce chapitre comporte trois boucles de contrôle (Figure IV-3) : •





Le contrôle du courant assure que chaque courant de branche ait les bonnes valeurs des composantes AC et DC nécessaires pour obtenir la puissance requise. Après avoir établi les équations électriques du MMC triphasé, nous exprimons les grandeurs électriques dans un repère tournant dq synchronisé sur le réseau alternatif. Une fois les équations établies dans ce nouveau repère, nous effectuons la synthèse des régulateurs PI de manière à ce que le système soit stable, capable de suivre la consigne de courant à la fréquence fondamentale et de supprimer la composante harmonique de courant de rang 2. En amont du contrôle de courant il faut assurer l’équilibre des énergies stockées dans les condensateurs. Compte tenu de la puissance mise en jeu côté continu, cette partie du contrôle adapte la puissance active afin de maintenir constantes les tensions sur les condensateurs des blocs. A cet effet un correcteur PI, dont nous donnons la synthèse, assure pour les branches positive et négative le contrôle de la valeur moyenne des tensions condensateurs. Dans une branche du convertisseur, les tensions sur chaque bloc peuvent être déséquilibrées à cause des dispersions sur les valeurs des composants passifs et des pertes différentes dans les semi-conducteurs. Pour cela, dans le but de réguler chaque tension condensateur à la valeur désirée, nous prévoyons un contrôle local basé sur un correcteur proportionnel qui agit sur le signal modulant au niveau de chaque bloc élémentaire. Des simulations, basées sur un convertisseur ayant des branches avec des pertes par blocs différentes, valident l’efficacité de ce réglage.

Chapitre V : Prototype de convertisseur modulaire multiniveaux de 10 kW. Afin de valider les résultats de calcul et de simulation, nous avons réalisé un prototype à puissance réduite. La structure inclut 18 cellules de commutation, elle est prévue pour fonctionner avec une tension DC de 600 V pour une puissance nominale de 10 kW (Figure Vxiii

Nicola Serbia 1). Cette maquette a été conçue et réalisée au LAPLACE. Le contrôle est implanté sur une plateforme DSP-FPGA. Nous testons une première configuration conformément à la Figure V-5. Nous considérons une branche unique par phase avec une charge RL triphasé de 4 kW en série, le tout est alimenté par une source de tension continue de 600 V. Après avoir étudié les boucles de contrôle et réalisé des simulations préliminaires, nous effectuons les tests en boucle fermée. Cette configuration a été initialement choisie car nous savons que la structure MMC classique, à deux branches par phase, peut difficilement limiter le courant en condition de défaut. Ainsi, la présence de la charge RL en série dans chaque branche limite « naturellement » le courant et permet sans danger la mise au point des chaines de mesure des signaux et la validation de la synthèse des régulateurs. La bonne correspondance entre les résultats expérimentaux et les simulations nous permet alors d’aborder le fonctionnement dans une configuration MMC classique mais dans un premier temps avec un contrôle en boucle ouverte (Figure V-20) sur une charge RL triphasée de 5 kW. Des simulations en boucle fermée avec un contrôle en boucle fermée dans un repère dq valident ensuite la synthèse des correcteurs pour le système de 10 kW (Figure V-16). Les simulations sont effectuées sur une charge RL triphasée (Figure V-20). Il nous reste à effectuer les tests en boucle fermée sur la maquette. Conclusions et Perspectives Aujourd’hui, les connexions HVDC constituent un élément de réponse aux besoins énergétiques mondiaux croissants. La technologie multiniveaux, associé au développement de semi-conducteurs haute tension contrôlés au blocage, va permettre aux convertisseurs de type onduleur de tension (VSC) de devenir la topologie la plus employée dans les systèmes HVDC. Toutefois, grâce aux avantages découlant de la facilité de mise en série des thyristors, les structures CSC restent encore mieux adaptées aux tensions élevées. A court terme, l’écart entre les deux topologies pourrait se réduire de manière significative grâce aux performances offertes par les thyristors blocables de type IGCT. Ces composants en boitier pressé présentent par rapport aux modules classiques plusieurs avantages : En cas de court-circuit dans une cellule, il n’y a pas de risque d’explosion du boitier et la structure monolithique de l’IGCT (single wafer) est plus adaptée pour l’encapsulation en boitier pressé qu’un ensemble de petites puces IGBT. Ce travail de thèse a porté sur des topologies convertisseurs modulaires multiniveaux. Pour les études préliminaires, nous avons proposé un « macro modèle », indépendant de la topologie des blocs élémentaires, qui a permis une analyse directe du fonctionnement et des simulations plus rapides. Le dimensionnement du convertisseur a été effectué pour deux stratégies de contrôle. La première considère seulement un contrôle de la composante fondamentale du courant de sortie mais entraîne la circulation d’un harmonique de rang deux dans les branches du circuit. La mise en œuvre d’inductances couplées dans les branches du convertisseur pourrait xiv

MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

constituer une bonne solution pour limiter ce courant mais dans la gamme de puissance visée (GW), une telle technologie augmenterait les coûts de manière considérable. En revanche, la seconde approche, consiste à contrôler le courant dans chacune des branches mais requiert un système de contrôle plus performant basé sur une commande en dq. A cette condition, la composante harmonique de courant de rang deux est supprimée, ce qui permet de minimiser le volume et donc le coût des éléments réactifs. L’emploi des différentes topologies de bloc élémentaire rend le MMC plus flexible en termes de réversibilité en tension et en courant. En termes de pertes, à niveaux de puissance et de tension continue identiques, la simple cellule est la plus intéressante. Cependant, les autres topologies qui fournissent une tension de sortie bipolaire (pont asymétrique et pont complet) rendent la structure apte à limiter le courant en cas de court-circuit côté continu. La commande MLI classique avec entrelacement des porteuses permet une réduction de la fréquence de commutation ce qui minimise les pertes dans les semi-conducteurs. Toutefois cette technique de modulation présente une limite inférieure en fréquence de commutation de l’ordre de 200 Hz. Quand le nombre de niveaux est très élevé, la modulation de la tension en « marches d’escalier » peut être très intéressante. Une étude de cette technique de modulation (marge d’escalier) sera développée prochainement. En effet, il nous reste à analyser l’impact de cette stratégie de modulation sur le dimensionnement des éléments réactifs et les pertes dans les semi-conducteurs pour la comparer à la commande MLI classique avec entrelacement des porteuses. Différents aspects pourraient rendre le pont asymétrique intéressant dans les applications HVDC. En effet, par rapport à la structure classique, pour une même amplitude relative d’ondulation de tension, la capacité du condensateur de chaque bloc peut être réduite. De plus, comme le système effectue l’inversion du flux de puissance par le changement de polarité de la tension DC, cette topologie peut être employée pour remplacer les structures CSC dans des sous-stations HVDC avec l’avantage de travailler à facteur de puissance unitaire. La nouvelle structure à une seule branche par phase (single loop) proposée dans le chapitre III permet un contrôle plus simple. Elle ne requiert pas d’inductances en série dans les branches puisqu’elle utilise directement l’inductance de fuite du transformateur dont le secondaire doit être couplé en zigzag pour annuler la composante continue du flux dans les colonnes. De plus l’isolement du transformateur est dimensionné uniquement pour la tension du réseau alternatif. Ceci n’est pas le cas de la configuration classique du MMC où, en plus de la composante alternative de tension, le transformateur doit supporter une tension d’isolement continue égale à la moitié de la tension sur le lien DC (composante homopolaire). Au-delà de ces considérations, et de manière plus générale, l’utilisation de cette nouvelle structure pourrait être intéressante pour remplacer d’anciens redresseurs à diodes ou à thyristors, en apportant les avantages découlant de la structure VSC. Un prototype de 10 kW a été développé au laboratoire LAPLACE. Afin d’interfacer le circuit de puissance avec le système de contrôle, un ensemble de cartes « Interface Hardware » a été réalisée. Cet ensemble de cartes adapte les niveaux des signaux provenant des capteurs du prototype aux niveaux des tensions d’entrée du dispositif de commande. Il permet aussi le xv

Nicola Serbia filtrage du bruit pour les signaux analogiques. En ce qui concerne les signaux numériques de commande en provenance du dispositif de contrôle, ceux-ci sont transmis aux cellules de commutation via des fibres optiques. Avant de démarrer les essais en puissance, une procédure préliminaire de test a été effectuée. Tous les capteurs ont été calibrés et toutes les connexions de la chaine de mesure ont été vérifiées. Enfin, l’interconnexion des masses de tout le système a été effectuée petit à petit afin d’éviter tout problème de compatibilité électromagnétique (CEM). Les résultats expérimentaux avec une commande MLI classique avec entrelacement des porteuses ont été obtenus pour la structure à boucle simple et la structure classique. Le bon fonctionnement des boucles de contrôle a permis de valider le modèle du système et la synthèse des régulateurs. Prochainement, ce prototype permettra d’une part de tester la structure à une branche par phase avec le transformateur à secondaire couplé en zigzag et d’autre part le fonctionnement en boucle fermée avec la commande en dq puis la modulation en « marche d’escalier ».

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RIASSUNTO DETTAGLIATO DELLA TESI IN LINGUA ITALIANA Capitolo I: A proposito di HVDC Questo capitolo tratta i sistemi HVDC (le transport d’énergie électrique en courant continu Haute Tension) andandone ad evidenziare il ruolo chiave che hanno nel campo della trasmissione dell’energia elettrica attraverso la consultazione di circa 40 riferimenti bibliografici. L’adozione di sistemi HVDC negli ultimi 40 anni ha avuto un ruolo fondamentale per i sistemi di trasmissione per una serie di considerazioni tecniche ed economiche. • Rispetto ai sistemi di trasmissione AC, trasmettere in corrente continua, nonostante il costo addizionale dovuto alle sottostazioni di conversione, inizia a diventare conveniente per distanze maggiori di 800 km per linee aeree e 50 km per linee sottomarine (Figure I-1). • Il continuo miglioramento delle tecnologie dei dispositivi semiconduttori essendo al cuore delle tecnologie HVDC • Sistemi in corrente continua consentono interconnessioni tra reti eterogenee che possono essere asincrone tra loro e/o a frequenza diversa. Una descrizione sui principi di connessione HVDC è stata illustrata facendo riferimento alle principali installazioni attualmente esistenti ciascuna delle quali in grado di gestire potenze dell’ordine dei GWs. Due tipi di connessione HVDC sono utilizzate. Quelle basate su convertitori AC/DC di corrente (CSC) e quelle basate su convertitori AC/DC di tensione (VSC). I lavori presenti nella letteratura corrente fino ad oggi si sono sempre focalizzati sulla topologia dei convertitori, in questo lavoro una delucidazione esaustiva sul concetto di trasferimento di potenza di tipo HVDC sia per strutture CSC che VSC è stata data. Prima di scendere nel dettaglio i principali dispositivi semiconduttori disponibili sul mercato ed impiegati per le alte tensioni sono stati descritti attraverso la consultazione di circa venti riferimenti bibliografici. Lo studio ha messo in luce le varie evoluzioni dei dispositivi dandone un’ordine di grandezza sulle tensioni e correnti nominali sostenibili per ciascuno di essi. Inoltre una descrizione dettagliata della tecnica presspack è stata data giacché tale tecnologia può essere considerata la meglio candidata per l’utilizzo e l’impiego di dispositivi semiconduttori nelle alte potenze. Una descrizione dei convertitori CSC basati su tiristori è stata fornita al fine di rendere meglio comprensibile l’approccio adottato per lo scambio di potenza per queste strutture. Grazie al fatto che i tiristori non presentano problemi di connessione diretta in serie, i sistemi CSC-HVDC riescono a raggiungere tensioni dell’ordine dei 500 kV. Ovviamente la topolgia non consente il controllo indipendente della potenza attiva e reattiva ed inoltre esibisce un

xvii

Nicola Serbia contenuto armonico in corrente tale da richiedere dispositivi di filtraggio che occupano il 2030 % della superficie totale di una sottostazione (Figure I-42). Una descrizione dei convertitori VSC modulati PWM (MLI) basati su dispositivi di commutazione controllabili sia in apertura che in chiusura (IGBT) è stata fornita. Dopodiché la trasmissione di energia HVDC basata su convertitori VSC è stata illustrata. Le topologie VSC riescono ad effettuare il trasferimento di potenza attiva e reattiva in maniera indipendente. D’altro canto per topologie classiche a due livelli si riesce al massimo ad operare a 320 kV a causa dei problemi dovuti alla messa in serie di dispositivi IGBT. Le topologie VSC sono state prese in considerazione nel lavoro. In particolare una descrizione delle strutture multilivello è stata data grazie alla loro capacità di lavorare ad alte tensioni. Tali topologie rispetto a quelle tradizionali riescono a garantire una forma d’onda quasi sinusoidale riducendo il contenuto armonico e permettendo una riduzione degli elementi di filtraggio. All’interno delle topologie multilivello la struttura modulare multilivello (MMC) è stata presentata nel capitolo e studiata nel lavoro di tesi. Tale struttura consiste nella messa in serie di convertitori elementari (Figure I-62) normalmente identici (per questo modulare). Tale struttura è stata preferita a quelle tradizionali giacché garantisce una modularità in termini di produzione industriale e non ha limitazioni superiori sul valore della tensione DC poiché è possibile sempre aggiungere convertitori elementari in serie. Capitolo II: Strutture modulari multilivello La struttura modulare multilivello è stata studiata in questo capitolo. La configurazione trifase per questa struttura è formata dalla connessione di due rami per fase (Figure II-1). Ogni ramo impone metà della tensione DC e la tensione al lato AC. Ciascun ramo inoltre conduce un terzo della corrente DC e la metà della corrente AC. La combinazione tra i due rami fa si che si ottengano le correnti e tensioni AC e DC necessarie al trasferimento di potenza richiesto. Per l’analisi un modello medio della struttura è stato estratto (macro modello) al fine di semplificare le considerazioni preliminari. Tale modello non considera gli effetti delle armoniche dovuti ai dispositivi di commutazione ma garantisce una maggiore velocità nelle simulazioni poiché semplifica i calcoli. Lo studio inoltre è stato ottenuto indipententemente dalla scelta della topologia per il convertitore elementare e considerando una phase shifted sinusoidal PWM (commande MLI classique avec entrelacement des porteuses). La potenzialità dello studio, oltre alla semplificazione della comprensione, sta nel fatto che tale struttura è stata resa altamente flessibile e versatile in termini di tensioni e correnti gestite. In una analisi preliminare correnti e tensioni del sistema sono state analizzate. Dal punto di vista armonico di corrente, ciascun ramo, oltre alle componenti DC ed AC conduce una componente AC al doppio della frequenza fondamentale che rimane all’interno della struttura (corrente circolante in Figure II-9). Questa componente deriva dal bilanciamento energetico tra i due bracci che compongono ogni fase. La soppressione di tale componente gioca un ruolo fondamentale nel dimensionamento dei componenti reattivi che è stata effettuata considerando due casi. Il primo caso considera un sistema controllato in maniera tale per cui non si è in grado di sopprimere l’armonica di II ordine della corrente di ramo. Per tale motivo la compensazione è xviii

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effettuata in maniera hardware. Al crescere del condensatore posto in parallelo a ciascun convertitore elementare e dell’induttore di ramo tale armonica si riduce. Per problemi di controllabilità del sistema dovuti ad elevati valori dell’induttore di ramo una nuova configurazione di tipo tripolare per l’induttore è stata proposta nel lavoro. Tale induttore è configurato in maniera tale da imporre una elevata induttanza di ramo al fine di sopprimere la II arminica nella corrente ed una ridotta induttanza di uscita garantendo la controllabilità del sistema. Tale approccio ovviamente richiede un hardware più costoso ma un controllo più semplice. Il secondo caso considera un controllo leggermente più complesso capace di controllare ciascuna corrente di ramo in maniera tale da ottenere il riferimento desiderato alla armonica fondamentale di corrente e di sopprimere anche la corrente circolante nel ramo alla seconda armonica della fondamentale. In tali condizioni il dimensionamento dei componenti passivi si riduce giacché solo l’armonica di corrente a frequenza fondamentale è considerata. La complicatezza del controllo non è un problema al giorno d’oggi grazie alla vasta scelta di dispositivi di controllo disponibili sul mercato. Per questo motivo è stato preferito in questo lavoro di tesi. Per tutti i casi, simulazioni su un sistema da 100 MW composto da 64 convertitori elementari per ramo hanno validato lo studio.

Capitolo III: Nuove topologie multilivello per sottostazioni HVDC In questa parte del lavoro nuove configurazioni per la struttura modulare multilivello sono state studiate e proposte. Ciò è avvenuto andando a cambiare di volta in volta la topologia del convertitore elementare. Disporre di differenti topologie ha reso la struttura MMC più versatile e flessibile nei confronti dei livelli di tensione e corrente. La prima topologia considerata come convertitore elementare è la cella semplice che rappresenta la versione base dell’MMC. Questa topologia è bidirezionale in corrente ma unipolare in tensione. Per tale motivo in condizioni di fault DC il sistema multilivello non è in grado di limitare la correne di corto circuito rischiando di danneggiare i dispositivi semiconduttori. Solo celle bipolari sono in grado di meglio limitare la corrente in condizioni di fault DC. A tale scopo il ponte asimmetrico ad H ed il ponte intero ad H sono stati considerati. La prima struttura (Figure III-8) è bipolare in tensione ma unidirezionale in corrente. Per tale motivo l’impiego di questa topologia rende la struttura MMC poco adatta a scambi di potenza reattiva. In condizioni di fattore di potenza unitario, essendo tale topologia unidirezionale in corrente, il sistema effettua l’inversione della potenza tramite l’inversione della tensione che è tipico dei sistemi CSC. Per questo motivo tale struttura può essere anche utilizzata per il rimpiazzo immediato di convertitori basati su tiristori. Infine tra le celle bipolari anche il ponte ad H è stato considerato (Figure III-11). Ovviamente tale struttura è la più flessibile delle prime due essendo anche bidirezionale in corrente ma esige il doppio dei componenti. In questa parte un approccio analitico per il calcolo delle perdite nei dispositivi è stato dato. Tale approccio ha reso la valutazione della efficienza del sistema diretta veloce. Tale approccio era stato evitato in letteratura giacché la componente continua della forma di xix

Nicola Serbia corrente nei dispositivi, dovuta alla struttura MMC, rendeva il calcolo delle perdite molto complesso. Nel presente lavoro invece la formalizzazione analitica delle perdite è stata formalizzata e validata. A valle della validazione delle forme analitiche tramite il software PSIM un confronto sul rendimento del sistema è stato effettuato considerando l’uso delle tre topologie evidenziate sopra. Il confronto è stato effettuato a parità di potenza (100 MW) e di tensione DC (160 kV). In termini di rendimento la singola cella è la meno dissipativa. Le altre due celle bi-polari hanno un incremento delle perdite giacché richiedono un incremento dei componenti, tali perdite non sono accettabili per i livelli di potenza gestita. Ovviamente tali topologie permettono al sistema di gestire meglio le condizioni di faults. Successivamente nel capitolo una nuova struttura modulare multilivello è presentata (Figure III-28) chiamata Raddrizzatore a singola semionda. Per ogni fase questa topologia adotta un solo ramo rispetto alla versione tradizionale. D’altro canto si interfaccia con la rete attraverso un trasformatore zig-zag. Il dimensionamento dei componenti reattivi e dei dispositivi semiconduttori è lo stesso della versione base. Al fine di validare lo studio del macromodello questa nuova struttura è stata proposta per rimpiazzare i vecchi raddrizzatori basati su diodi o tiristori (Figure III-30). Il rimpiazzo è stato sviluppato conservando lo stesso trasformatore di linea e dunque gli stessi livelli di corrente e tensione. Simulazioni sono state effettuate considerando un sistema da 10 MVA. Capitolo IV: Un nuovo controllo PWM per le strutture modulari multilivello Un nuovo controllo per le strutture MMC è stato sviluppato in questo capitolo considerando una modulazione (commande MLI classique avec entrelacement des porteuses). Volta per volta simulazioni hanno validato lo studio considerando un sistema da 100 MW con una tensione DC di 160 kV. Le simulazioni sono state inoltre fornite per condizioni di funzionamento a fattore di potenza unitario in modalità inverter e raddrizzatore. Il controllo dei sistemi MMC in letteratura hanno sempre cercato di sopprimere la seconda armonica di ramo della corrente in maniera parallela al controllo tradizionale. Ci sono numerosi lavori che adottano tale sistema rendendo il controllo alquanto complesso sia alla comprensione che all’implementazione [49]-[51]. Il controllo tipico per i sistemi multilivello è costituito da tre cicli di controllo fondamentali (Figure IV-3). • Il controllo di corrente , assicura che ciascuna corrente di ramo abbia i giusti valori per le componenti AC e DC necessare ad ottenere la potenza richiesta. L’approccio per tale controllo è stato effettuato tramite una sovrapposizione degli effetti. Dopo aver impostato le equazioni caratterizzanti il sistema è stata effettuata una trasformazione delle grandezze nel sistema di riferimento ad assi rotanti DQ. Una volta definite le equazioni, la sintesi dei regolatori PI è stata effettuata in maniera tale rendere il sistema in grado di inseguire la corrente desiderata e sopprimere la seconda armonica di corrente (corrente di ricircolo) nei margini di stabilità.

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Il sistema di controllo proposto nel lavoro di tesi è lineare ed, attraverso la taratura dei regolatori, agisce in maniera tale da sopprimere anche la seconda armonica a frequenza fondamentale di corrente. L’innovazione sta nel fatto che il tutto è effettuato attraverso un singolo ciclo senza l’aggiunta di loops addizionali adottati in [50]-[51].

• A monte del controllo di corrente è posto il bilancio di energia di ramo. Tale parte di controllo regola la potenza attiva necessaria a mantenere tutte le tensioni sui condensatori di ramo costanti al valore desiderato. La sintesi dei regolatori PI è stata fornita. • Ciascuna cella di ramo può essere sbilanciata a causa delle differenti tolleranze dei componenti passivi, conduzioni diseguali e/o perdite differenti nei dispositivi semiconduttori ed infine differenti risoluzioni dei sensori. Per questo motivo al fine di bilanciare ogni cella al valore di tensione desiderato, un controllo locale è stato previsto definito come il bilancio della tensione di cella. Un correttore proporzionale per ogni convertitore elementare è stato adottato e sintetizzato. Tale controllo in maniera indipendente dai due precedenti agisce direttamente sull’indice di modulazione. Simulazioni in condizioni di celle sbilanciate hanno validato lo studio. Capitolo V: Il prototipo MMC da 10 kW Al fine di validare i risultati analitici e simulativi un prototipo a potenza ridotta è stato realizzato. Tale struttura include 18 celle di commutazione di tipo semplice (simple cell), una tensione DC di 600 V ed una potenza nominale di 10 kW (Figure V-1). Il prototipo è stato progettato e realizzato presso il LAPLACE. Inoltre al fine di effettuare i test sperimentali il controllo è stato implementata tramite piattaforma DSP-FPGA. I livelli di potenza e di tensione scelti per il prototipo sono abbastanza alti per una rispetto a quelli adottati in letteratura per la sperimentazione da laboratorio di sistemi MMC. Una prima configurazione in modalità single loop è stata testata (Figure V-5). In particolare solo un ramo per fase si è considerato con in serie un carico RL da 4 kW. Il tutto in parallelo alla sorgente DC. Dopo la sintesi del controllo e simulazioni preliminari, sono stati effettuati tests a ciclo chiuso. Questa è una configurazione intermedia che ha un duplice scopo. È noto che la classica struttura MMC è poco capace di limitare la corrente di ramo in condizioni di faults, per questo motivo non è stata preferita come prima prova. La presenza del carico RL in serie al ramo infatti limita la corrente nel ramo garantendo lo stesso un set-up delle catene di segnale e la validazione della sintesi dei regolatori in condizioni di sicurezza. È definita configurazione intermedia giacché a causa delle proprietà unipolari della cella semplice al carico viene imposta anche una componente DC all’interno del ramo. In ogni caso la buona corrispondenza tra simulazioni e prove sperimentali hanno reso il passaggio alla configurazione con trasformatore zig-zag immediato. In un secondo step la struttura MMC a ciclo aperto è stata considerata (Figure V-20). Simulazioni preliminari a ciclo chiuso con un controllo nel sistema di riferimento rotante DQ hanno validato la sintesi dei controllori per il sistema da 10 kW (Figure V-16). Le simulazioni sono state effettuate imponendo la rete al lato AC. Il sistema è stato dunque testato in xxi

Nicola Serbia modalità raddrizzatore e inverter a fattore di potenza unitario. Successivamente prove sperimentali a ciclo aperto sono state effettuate imponendo al sistema un carico RL di circa 5 kW (Figure V-20) al fine di validare la giusta modulazione e il corretto dimensionamento dei componenti reattivi (condensatori ed induttori). Resta da effettuare ovviamente il passaggio dei test a ciclo chiuso per la struttura MMC. Conclusioni e Prospettive Al giorno d’oggi le connessioni HVDC sono una buona risposta alla fabbisogno energetico mondiale che è sempre più crescente. Le topologie multilivello stanno rendendo i Voltage source converters (VSC) tra i più impiegati nei sistemi HVDC. Lo sviluppo dei dispositivi semiconduttori controllati in fase di spegnimento ed impiegati per alte tensione hanno reso queste strutture molto interessanti. D’altro canto grazie ai vantaggi derivanti dalla facilità della messa in serie di tiristori, le strutture CSC gestiscono meglio le alte tensioni. Nel prossimo futuro, il divario tra le due topologie verrà decisamente ridotto grazie alle prestazioni offerte dai dispositivi IGCT sia nella fase di accensione che di spegnimento. L’inscatolamento a pressione (press pack) porta inoltre una serie di vantaggi rispetto ai moduli classici specialmente in condizioni di emergenza dove c’è il rischio di esplosione. La struttura a singolo tassello (single wafer) rende l’IGCT più adatto per l’inscatolamento a pressione rispetto all’IGBT. Per queste ragioni l’IGCT sembra essere il dispositivo più attrattivo in applicazioni VSC-HVDC. Il lavoro di tesi è stato focalizzato sui convertitori modulari multilivello. Per studi preliminari il “macromodello” ha consentito valutazioni dirette e simulazioni più veloci. Inoltre ha reso il modello indipendente dalla particolare topologia. Il dimensionamento del sistema è stato effettuato attraverso due approcci di controllo. Il primo considera solo un controllo sulla corrente di uscita AC che determina una considerevole seconda armonica nel ramo. L’induttore tripolare accoppiato potrebbe essere una buona soluzione al fine di limitare questa corrente ma nel campo delle applicazioni di alta potenza, la particolarità dell’hardware accresce i costi in maniera considerevole. Il secondo approccio invece consiste nel controllo della corrente di ciascun ramo, inoltre esso richiede un sistema di controllo più efficiente basato sul sistema di riferimento rotante DQ. Sotto questa condizione la seconda componente armonica della corrente è cancellata andando a ridurre i costi degli elementi reattivi. L’impiego di differenti topologie come convertitore elementare rende l’MMC più flessibile in termini di reversibilità di tensione e corrente. In termini di perdite a parità di potenza e tensione DC, la cella semplice è più conveniente. Le altre topologie però che forniscono una tensione bipolare (HB asimmetrico e ponte ad H) rendono la struttura capace di limitare la corrente di corto circuito in caso di fault DC. La commande MLI classique avec entrelacement des porteuses porta ad una riduzione della frequenza di switching e dunque riduce le perdite nei dispositivi. Certamente questa tecnica di modulazione presenta un limite inferiore sulla frequenza di switching. Quando il numero dei livelli è molto elevato la modulazione stai case (marge d’escalier) può essere molto interessante per strutture multilivello. Uno studio della modulazione (marge d’escalier) sarà xxii

MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

presto sviluppato. Infatti rimane da fare una investigazione sugli effetti della modulazione nei confronti del dimensionamento di elementi reattivi e nei confronti delle perdite nei dispositivi rispetto alla (commande MLI classique avec entrelacement des porteuses). Differenti aspetti potrebbero rendere il ponte asimmetrico ad H interessante nelle applicazioni HVDC. Se questa topologia è scelta, il condensatore di cella potrebbe essere ridotto a parità di ampiezza di oscillazione della tensione. Siccome il sistema effettua l’inversione del flusso di potenza tramite il cambiamento della polarità della tensione DC, questa topologia può essere impiegata per rimpiazzare strutture CSC per sottostazioni HVDC con il vantaggio di lavorare a fattore di potenza unitario.

La struttura nuova a controllo unico (single loop) proposta nel capitolo III permette un controllo più semplice. La topologie non richiede il doppio induttore poiché utilizza l’induttore parassita posto in serie al trasformatore accoppiato zig-zag. l’accoppiamento del trasformatore richiede più rame di un classico avvolgimento. L’isolamento del trasformatore deve essere effettuato solo per la tensione AC. Questo non è il caso della classica configurazione per l’MMC dove il trasformatore deve sostenere un isolamento DC pari alla metà della tensione sullo DC link (sequenza omopolare). Oltre a queste considerazioni, l’uso di questa nuova struttura potrebbe essere interessante per rimpiazzare i vecchi raddrizzatori garantendo i vantaggi derivanti dalle strutture VSC. Un prototipo da 10 kW è stato sviluppato nel laboratorio LAPLACE. Al fine di interfacciare il circuito di potenza con il sistema di ptototipazione rapida, una piattaforma di schede piazzate sulla struttura chiamata “Hardware di Interfaccia” è stata realizzata. Questo hardware adatta i livelli dei segnali provenienti dai sensori del prototipo verso il livello delle tensioni di ingresso del dispositivo di pototipazione rapida. Inoltre tale hardware fornisce il filtraggio del rumore per i segnali analogici. Anche per i segnali digitali provenienti dal dispositivo di prototipazione, una conversione elettro-ottica è stata fornita dall’hardware di interfaccia al fine di controllare le celle. Prima di avviare le prove in potenza, una procedura preliminare è state eseguita. Tutti i sensori sono stati calibrati e la giusta connessione della catena di segnale è stata verificata. Infine l’ottimizzazione della configurazione delle masse di tutto il sistema è stata effettuata passo dopo passo al fine evitare tutti i probleme dovuti alla compatibilità elettromagnetica (EMI) Risultati sperimentali in (commande MLI classique avec entrelacement des porteuses) sono stati ottenuti per la struttura a singolo ciclo e quella classica. Il buon funzionamento dei cicli di controllo ha validato il modello del sistema e la sintesi dei regolatori. Prossimamente, questo prototipo permetterà di testare la struttura a singolo ciclo con il trasformatore zig-zag, il funzionamento a ciclo chiuso nel sistema di riferimento dq e la modulazione a (marge d’escalier).

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Content Chapter I. 

HVDC SYSTEMS ....................................................................................... 1 

I.1 

About HVDC...................................................................................................... 1 

I.2 

HVDC Connection Systems ................................................................................ 3 

I.2.1 

The concept of a HVDC connection ............................................................. 3 

I.2.2 

HVDC Configurations ................................................................................. 7 

I.2.3 

Semiconductor devices for HVDC systems ................................................... 8 

I.2.4 

CSC-Phase controlled converters ................................................................ 16 

I.2.5 

CSC-HVDC SYSTEMS ............................................................................. 20 

I.2.6 

VSC-PWM based AC/DC converters......................................................... 21 

I.2.7 

VSC-HVDC systems .................................................................................. 26 

I.3 

VSC-HVDC multilevel topologies ..................................................................... 27 

I.3.1 

Neutral Point Clamped (NPC) ................................................................... 29 

I.3.2 

Flying capacitor ......................................................................................... 29 

I.3.3 

Cascaded Multilevel Inverters .................................................................... 31 

I.4 

Conclusions ...................................................................................................... 32 

Chapter II. 

MMC systems............................................................................................ 33 

II.1  The Macro Model ............................................................................................. 34  II.1.1 

Macro model validation ............................................................................. 36 

II.1.2 

Study of the MMC basic structure .............................................................. 38 

II.2  Output current imposition ................................................................................. 40  II.2.1 

Cell capacitor ............................................................................................. 42 

II.2.2 

Branch inductor ......................................................................................... 43 

II.2.3 

Simulations ................................................................................................ 48 

II.3  Branch current imposition ................................................................................. 53  II.3.1 

Sizing ........................................................................................................ 54 

II.3.2 

Simulations ................................................................................................ 54 

II.4  Conclusions ...................................................................................................... 57  Chapter III.  New multilevel topologies .......................................................................... 59 

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III.1 

Elementary converters for the MMC Structure ............................................... 60 

III.1.1  Single Cell ................................................................................................. 62  III.1.2  Asymmetrical H-bridge .............................................................................. 64  III.1.3  H-bridge..................................................................................................... 66  III.2 

Efficiency for multilevel structure ................................................................... 67 

III.2.1  The analytical approach ............................................................................. 68  III.2.2  System rating ............................................................................................. 68  III.2.3  Single cell& Full H-Bridge .......................................................................... 69  III.2.4  Asymmetrical H-Bridge .............................................................................. 75  III.3 

Conclusions ................................................................................................... 77 

III.4 

New Multilevel active front end topology with zigzag transformer .................. 78 

III.4.1  New Multilevel active front end topology to upgrade three phase half wave rectifiers Erreur ! Signet non défini.  III.4.2  Conclusions ............................................................................................... 85  Chapter IV. 

PWM Control for Modular Multilevel Converter .................................... 87 

IV.1 

Introduction .................................................................................................. 88 

IV.2 

Principle of the Phase shifted PWM for MMCs .............................................. 89 

IV.2.1  Current control loop ................................................................................... 91  IV.2.2  dq0 reference frame .................................................................................... 94  IV.2.3  Branch energy balancing .......................................................................... 102  IV.2.4  Cell voltage balancing .............................................................................. 105  IV.3  Chapter V. 

Conclusions ................................................................................................. 108  The 10 kW modular multilevel prototype ................................................. 109 

V.1  The prototype configuration ............................................................................ 110  V.1.1 

Reactive elements design .......................................................................... 111 

V.1.2 

Hardware In the Loop configuration ........................................................ 112 

V.2  Single Loop Configuration .............................................................................. 114  V.2.1 

The control .............................................................................................. 116 

V.2.2 

Simulations .............................................................................................. 118 

V.2.3 

Experimental results ................................................................................. 120 

V.3  MMC configuration ........................................................................................ 121  V.3.1 

Simulations in Closed Loop operation ...................................................... 121 

V.3.2 

Open Loop-Tests...................................................................................... 124 

V.4  Conclusions .................................................................................................... 130  xxv

Nicola Serbia A.1  The Elementary cell ........................................................................................ 133  V.4.1 

Measurement Cards ................................................................................. 135 

A.2  The Frame ...................................................................................................... 136  A.1.1 

Acquisition Card ...................................................................................... 141 

A.1.1 

Optical emitter ......................................................................................... 142 

A.2  HIL Box ......................................................................................................... 143  A.3  PIN tables ....................................................................................................... 144 

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Chapter I.

HVDC SYSTEMS

This chapter presents the HVDC systems by pointing out the key role that they play in the field of electrical energy transmission. After a chronological description of the penetration of the HVDC system in the transmission grid scenario, the most employed structures are depicted and their advantages/drawbacks are described. A comparison is achieved between the Current Source Converter and Voltage Source Converter based HVDC. Nowadays, regarding economic and technical considerations VSC-HVDC systems are most popular. Then, this work focuses on the topology based on Modular Multilevel Converters (MMCs) which is more and more often chosen for VSC-HVDC power stations

I.1 About HVDC The world energy consumption is expected to increase by more than 54% every ten years [1]. Moreover, population growth and the development of “new economies” require energy sharing that has to keep in step to guarantee electrical grid voltage stability. On the other hand, the Kyoto protocol to the United Nations framework convention on climate change defined the ways and the constraints of regulating energy production. Those in attendance at this meeting considered renewable energy sources as a good way to achieve the goal. Since the beginning of the 21st century, many countries have chosen to deregulate the electricity sector. This has created a more flexible mix of energy sources by encouraging higher efficiencies, particularly with the introduction of private investments in the energy market. In the scenario of electrical energy transmission growth, HVDC systems seem to best meet the purposes given. As affirmed in [1], thanks to their inherent power flow control capability and asynchronous feature, HVDC systems associated with flexible AC transmission systems (FACTS) are spreading all over the world. In the last 40 years, HVDC has played a key role in transmission systems with a series of economic and technical considerations: •

As shown in Figure I-1, compared to AC transmission systems, HVDC transmission systems become more convenient for a distance depending on the line technology (around 800 km for overhead line and 50 km for underground or 1

Chapter I

HVDC Systems submarine cables). Despite the fact that HVDC converter stations are expensive, the transmission line requires a reduced number of conductors which approximately leads to a reduction of one third of the cost.

Cost

Break Even Distance DC converter station

DC

AC AC station 800-1000 km 50 km Overhead Line Submarine cables Distance

Figure I-1 - Estimation of the coasts for AC and DC transmission



The ever-increasing improvements in power electronics devices, more particularly in the field of turn-off controlled semiconductors, are at the heart of HVDC technologies [2].



HVDC systems allow interconnections between miscellaneous grids which can be asynchronous or with different operating frequencies. They facilitate integration of renewable sources like wind farms or photovoltaic plants.

Until 2005, according to [3], the total power installed in HVDC systems was around 55 GW, amounting to 1.4% of the worldwide installed generation capacity. The curve shown in Figure I-2 shows the trend of the main installations achieved in the world since 1970. In the next years, 48 GW of HVDC installed stations are expected by China alone. A detailed overview on the existing project can be further found in [4].

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Figure I-2: Power provided by HVDC transmissions

I.2 HVDC Connection Systems I.2.1

The concept of a HVDC connection

The evolution of the solid state devices essentially made possible the concept of the AC/DC conversion. The mercury arc valves were replaced by solid-state devices named thyristors since 1970s. The first thyristor employment was the Eel River in Canada based on Line-Commutated Converter (LCC), which was built by General Electric and went into service in 1972 [5]. Since that time onwards, the thyristor LCCs or Current Source Converters (CSCs) have been continuously diffusing and developing for HVDC applications, like the transmission systems for which the basic configuration is shown in Figure I-3. The typical CSC based HVDC connection assumes in steady state that the power flow is regulated by changing the sign of the averaged value of the voltages (Vout1 and Vout2 ) imposed on the DC line. The system is adopted for high power levels, beyond 1 GW, for installations like the Itapiu system in Brazil (6.3 GW) [6], or the longest power transmission that links Xiangjiaba to Shanghai [7].

v Reactive Power

IDC

i

vout1

vout2

i

v Reactive Power

Real Power Figure I-3 - CSC-HVDC system base lay out

3

Chapter I

H HVDC System ms

In TABL LE I-1 exam mples of existing CSC-H HVDC conn nections are listed. The table gives an idea of the power, leveel voltages an nd the transm mission disttances insure ed by these systems.

Project Nam me France England Shin-Shinan no Sakuma Norway Netherland d Xiangjiabaa Shanghai

Compleetation Yeaar

wer Rating Pow

DC voltage

Covered Distance

Maker

Semiconducttor devices

198 86

2 GW

±270 kV

70 km

Alstom Grid

Thyristorss

199 93

0,3 0 GW

±125 kV

Mitsubishi M

Thyristorss

200 08

0,7 0 GW

±450 kV

580 km

ABB®

Thyristorss

201 10

7.2 7 GW

±800 kV

1900 km

ABB®

Thyristorss

TABLE I-1: Example of E Existing CSC-H HVDC connections

The hugge DC voltaage that thesse converterrs can reach is allowed thanks t to thhe direct serries connection n of the thyrristors. More detailed d descriptions on the deviices are giveen in the neext section. Jusst to give an n idea of thee huge physiical structure, an examp ple in series connection of 336 thyristo ors such as the Shin-Sh hinano substtation is giv ven in Figure e I-4. Anothher examplee is also given iin Figure I-5 5. It corresp ponds to the substation located in France F (Les mandarins) of the France – England HVDC H interrconnection .

Figurre I-4: thyristorr tower for the frequency cconverter on Sh hin-Shinano side Figurre I-5: Thyristor tower of the F France-Englan nd connection on the french side

Howeveer, the devellopment of high h rated fu ully controlllable switche es, which arre described in the next seection, such h as insulatted gate bippolar transisstors (IGBT Ts) and gatee-commutatted

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thyristors (IGCTs) let the Voltage Source Converters (VSCs) be an attractive alternative to the CSCs for HVDC applications. The level of power afforded for these systems goes hand in hand with the evolution of the VSC topologies and the voltage which the semiconductor device is able to sustain. A basic configuration of these connections is shown in Figure I-6. In steady state the power flow is regulated by changing the sign of the averaged value of the currents imposed on the DC line. The first VSC-HVDC installation, which consolidated the success of these systems, was the HVDC Hellsjön–Grängesberg (Sweden) from ABB, called HVDC Light [8]. It is a PWMcontrolled system built at the beginning of 1997 [1]. The power rating is about 3 MW with a voltage of 10 kV. Many other installations are listed in [9].

Figure I-6 - VSC-HVDC system base layout

First VSCs for HVDC applications were two-level inverters while three-level inverters (Neutral Point Clamped topology) were introduced later. To sustain the huge voltage the installations are composed by series connected IGBTs. ABB is the only maker which provides this configuration (Figure I-7 and Figure I-8) [10]. The configuration allows each VSC to sustain maximum 320 kV with a maximum power rating at one GW.

Figure I-8: IGBTs Series connected lay-out Figure I-7: Typical series valve tower of ABB

5

Chapter I

H HVDC System ms

The lastt generation n of multilev vel VSC forr HVDC ap pplications is the Moduular Multilev vel Converter (MMC or M2C), M intro oduced by M Marquardt and a Lesnica ar in 2002, [11]. The fiirst n of MMC for HVDC C was the T Trans Bay Cable C in Sa an Franciscco, Californ nia, application powered byy Siemens in i Novembeer 2010, [122]. Another example off VSC HVD DC connectiion based on M MMC topollogy is the France-Spai F in interconn nection “INELFE” [13]] (Figure I-9). The connecction is ach hieved with a DC voltagge of ±320 kV and involves two cconverters of 1 GW each o one. In Figu ure I-10 is deepicted a typpical tower provided p for a phase of tthe MMC. An A overview of a typical MMC M based substation ffor HVDC connections c is shown inn Figure I-9.

Figure II-9: Lay out off a HVDC sub-station based oon MMC topology proposed p by SIE EMENS

Figure I-10: I typical MM MMC tower of a phase based on IGBT andd proposed by SIEMENS

In [1] iis affirmed that the CSC-HVDC C systems, also called “classic “ HV VDC”, can be considered as mature technologies t s today [14] -[18]. Advantages inclu ude their nattural ability to limit the ccurrents in fault condiitions on th he DC link k. In the pa ast, the inabbility of VS SC structures tto limit DC C currents under fault cconditions liimited theirr adoption. Of course the t CSC-HVDC connectio ons allow th he system w working at higher h DC voltages suchh as ±500 kV. k This becau use the seriees connectio on of thyristtors is well mastered. Today, T for tthese reason ns, only Ultra H HVDCs aree based on th hyristor convverters [16]. A more detailed description off the problem ms which the series connections of IGBTs lead d is given in [18]. There are a many reasons which h justify thee success off VSC structtures. We can c mention neew developments in ciircuit breakeers (CB), in n control sy ystems whicch are able to regulate thee DC voltagges not also in ordinaryy conditions [19]. Moreo over system ms which allo ow 6

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the power reversibility through the changing of the current direction require a less expensive cable technology than the others [20] (CSC-HVDC systems allow the change of the power flow through the changing of the DC voltage polarity).

I.2.2

HVDC Configurations

Different configurations of HVDC systems can be determined according to the particular application and the project considered. The main configuration lay outs are shown in this section. Then the methods to regulate the power flow are described for CSC and VSC systems. Back-to-back systems are composed of two converter stations. The conversion takes place in the main location, and these systems are not suitable for long-distance transmission. The block diagram depicted in Figure I-11 shows AC/DC conversion. This facilitates the connection between asynchronous grids. This kind of connection is also known as a unipolar system. Unipolar systems can be employed also for submarine connections by using the ground to return current. On the other hand many problems can be led from this kind of employment [9].

Figure I-11 – B2B HVDC system

One of the most used configurations is as shown in Figure I-12. These systems are mainly employed to transmit power in overhead lines. Also called bipolar systems, these are composed of two unipolar structures. Usually the double structure can be considered to be a redundancy. Of course if one of the two converters turns off, half part of the total power can be guaranteed on the line [9]. This structures use the ground as potential reference.

7

Chapter I

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Figure I-12: Bipolar system

By connecting more than two sets of converters, it is possible to arrange multi-terminal connections Figure I-13. For the particular depicted configuration converters, if CSC based connections are considered, 1 and 3 operate as rectifiers while converter 2 can operate as inverter. By mechanically switching the connections of a given converter, other combinations can be achieved [9]. For VSC based connections the switch is not necessary due to the sign of the DC voltage is kept.

=

≈ =





=

AC3 AC1

AC2



≈ =

= =



Figure I-13: Multi-terminal connection

I.2.3

Semiconductor devices for HVDC systems

Despite the huge cost of devices employed for the medium and high power applications, this kind of application covers only a much reduced part of the semiconductor total market [21] as shown in Figure I-14. The distribution and the trend of the semiconductors in power electronic field are reported in Figure I-15. The description indicates the manufacturer and places the semiconductor devices according to voltage and current rating.

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MW (1 B$)

kW Total 20 (B$)

W

mW Figure I-14: Total semiconductor market (2012) Figure I-15: Distribution and trend for semiconductor devices in power electronic field [22]

An investigation on the most used semiconductor devices was provided for the HVDC connection's field. For each device the operating range was given in terms of managed power, moreover advantages and drawbacks which decided the replacement of one respect to one another were highlighted. In [23] is affirmed that the device manufacturers have developed different technologies for addressing the demand for an increasing reliability and lifetime. In this context, the device packaging assumes a critical role. Several manufacturers prefer power modules with bonded interconnections even though these bonding wires and solder layers are susceptible to thermomechanical stress and ultimately failure when subjected to power cycling. In the high power electronic, particularly in HVDC field, a consolidated packaging structure is the press contact assembly technology [24] called Press-pack (PP). This technology achieves the conduction on the power side of the semiconductor junction through pressure contact surfaces. This leads to eliminate bonding wires and solder layers; it offers an improved power cycling lifetime [23]. According to the type of device, different technologies were developed by the makers such as single wafer (Figure I-16) PP or multi-die device PP (Figure I-17).

Figure I-17: Example of Press-Pack multi-die device

9

Chapter I

HVDC Systems Figure I-16:Cross section of a press-pack single wafer (monolithic)

Typical frame assemblies are provided for the single wafer press-pack and for multi die device in Figure I-18 and Figure I-19.

Figure I-18: Press-pack single wafer tower by ABB® Figure I-19: Assembled Press-Pack multi-die device

I.2.3.1 Diode For HVDC connections the fast diodes for the free-wheeling and the clamping ones are used according to the topology. The operating voltage range for the single device is about 1-10 kV. Moreover these devices can reach currents of 2-7 kA. The device is almost composed by a monolithic junction even for Press-Pack structures. Problems due to the reverse recovery are well treated in literature especially for the free willing diodes. Unexpected problems are caused by this phenomenon such as overvoltage and HF oscillations which lead to EMI problems. The most frequent problems are the “Snappy Recovery” (Figure I-20-a) and “Reverse Recovery Dynamic Avalanche” (Figure I-20-b). The study of these phenomena were been consolidated in [26] which showed that under adverse combinations of high commutating di/dt, large circuit stray inductance, low forward current and low junction temperature, it is likely that all fast power diodes produce excessive voltage spikes due to snappy recovery. One of the last high voltage diode technology is proposed by [26] and exhibits soft recovery performance under all operating conditions. This diode structure is capable of providing the necessary charge for soft recovery behavior by employing the new Field Charge Extraction (FCE) technology. More detailed aspects are treated in [21]-[27].

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Figure I-21: Reverse recovery voltage and current in the FCE diode Figure I-20: Reverse recovery voltages and current in the diodes (ABB®)

This FCE diode provided a new performance for high voltage fast recovery diodes and it can be considered as the most employed in applications based on fully-controlled semiconductor devices such as VSCs.

I.2.3.2 Thyristor These devices that can sustain voltages in the range of 10kV are matched for HVDC applications. On the market it can be found devices which can conduct current levels up to 5kA. Nevertheless, the thyristor is not a fully controllable switch. For HVDC applications, this device is usually provided in a Press-Pack single wafer structure (monolithic) (Figure I-22). Evolutions of power rating and wafer dimension versus time are reported in Figure I-23.

Figure I-22: Typical commercial thyristors (Infineon®) Figure I-23: The most powerful semiconductor type

Thyristors can reach very high voltage levels, they are very fast during turn-on and they don’t show overvoltage problems in series connection [28]-[22].

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I.2.3.3 IGBT The Insulate Gate Bipolar Transistor was introduced in 1981 combining a MOS gate with a bipolar transistor for high voltage sustaining and simple gate driving. Actually on the market there are devices which can sustain a voltage up to 6.5 kV and switch a current up to 750 A. This device thanks to the MOS gate can be controlled with a small power level. Moreover the MOS structure, distributed over the entire chip, allows full area conduction of the bipolar transistor.. For high high voltage and high current applications modules are based on multichip substrates (Figure I-24). The bi-directionality in current is guaranteed by the reverse diode which is included in the structure. An example of multi-chip packaging is given in Figure I-25. In many cases the fault of this component due to over-current makes the device always opened, which leads to an explosion [29]. For series connection of these devices, an external mechanical switch or a semiconductor device are always added to by-pass the broken device [30].

Figure I-24: Multi chip configuration proposed by ABB

Figure I-25: External package proposed by ABB for a multi chip configuration

For HVDC applications also the Press-Pack could be adopted. Nevertheless, as discussed in [23] the single wafer construction cannot be directly transferred to the manufacturing of IGBTs. Indeed, it is still not feasible to produce a large IGBT wafer for high power applications due to the fine pattern of the IGBT cell structure. To overcome this technological limitation, the press-pack housing for IGBT was developed as a multi-die device. Nowadays two Press Pack technologies can be found on the market [22], [31]. •

Direct Pressure

Proposed by Toshiba and Westcode, the system consists of several chip stacks each composed of an IGBT die, supporting molybdenum disks and a chip frame to align these disks. The external lids are also achieved with multi-blocks (stamps) transferring the external force to the individual IGBT stacks [22].

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Figure I-26: 3D lay out of a Direct pressure IGBT (Westcode)

Figure I-27: Westcode internal disposition of a IGBT

In [23] it was proved that the press-pack package shows excellent performances in terms of reliability and thermo mechanical-behaviors. On the other hand, according to the structure lay-out shown in Figure I-28, the direct transmission of the pressure to the single chip requires a calibration of the strength with high resolution due to the fragile structure of the single chip. Moreover an unbalanced distribution of the pressure among the chips directly decreases the reliability.

Figure I-28: Lay out of the IGBT in the frame



Indirect pressure

This technology was introduced by ABB that is the only maker, the structure is also called Press Pack Indirect (PPI). As reported in [32] - [33] a module consists of a number of parallel connected subassemblies, called “sub-modules” inside a rigid frame. As reported in Figure I-29, when the module is mechanically clamped, each of the press-pins is subject to a force F=c∆x, where c is the spring constant and ∆x is the travel distance. The surplus force, exceeding the sum of all forces on the chips, is sustained by the rigid frame. In this way, the difference in the force on the chips no longer depends on the pressure homogeneity in the stack, but only on internal tolerances of spring constant and travel distance, which can be accurately controlled.Thus, even long stacks, with their inherent problem of having

13

Chapter I

HVDC Systems

inhomogeneous pressure distribution across the PPI, become easy to assemble. In Figure I-30 a typical press-pack made by ABB and a tower of series connected IGBSs are reported.

Figure I-29: Three individual press-pin each

IGBT

chips

with

an Figure I-30: Pictures of a module stack, an open individual module, and a sub-module inside the module

It’ is well known that the Press-Pack IGBT modules proposed by ABB have a good resistance to the thermal cycling and allow a stable short circuit in fault conditions [34]. The indirect pressure of the construction presents better performances in case of high number of series connected devices. The homogeneous pressure distribution guarantees improvements in terms of thermal behaviors and gives to the structure a good robustness toward the vibrations. The modular structure leads to a good efficiency in terms of industrial production.

I.2.3.4

IGCT

The Integrated Gate-Commutated Thyristor is exclusively used for very high power applications such as medium voltage drives or wind turbine converters in the multi-megawatt range. These devices can turn-off up to 6 kA under 4.5 kV. In the future, this device could be the best candidate for HVDC systems based on VSCs. In the world-wide, there are only three production sites which are located in Japan (Mitsubishi), in Switzerland (ABB) and in Czec Republic (ABB). The IGCT presents a Monolithic structure (Figure I-31) always in press pack packaging as shown in Figure I-32.

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Figure I-31: 4" IGCT (5.5 kA/4.5 kV) (ABB)

Figure I-32: 6" IGBT wafer

As reported in [35] in the conducting state, an IGCT is a regenerative thyristor switch like a SCR or a GTO as illustrated in Figure I-33. In the blocking state, the gate cathode junction is reverse-biased and is effectively “out of operation” so the resultant device is that of Figure I-34.

Figure I-33: Lay out in conduction mode for the IGCT

Figure I-34: Lay out of the IGCT in blocking mode

Figure I-33 and Figure I-34 also represent the conducting and blocking states of GTOs with one major difference, namely that the IGCT can transit from a state to other one instantaneously [35]. A typical turn off phase for an IGCT device is shown in Figure I-35. . The IGCT technology allows eliminating the GTO zone [28] so the device becomes a transistor prior having to sustain any blocking voltage. Because turn-off occurs after the device has become a transistor, no external dv/dt limitation is required and the IGCT may operate without snubber as does a MOSFET or an IGBT [35].

15

Chapter I

HVDC Systems

Figure I-35: Typical currents and voltages for a IGCT in turn off mode

More detailed aspect in terms of devices presents on the market and their dimension, operative voltage and current are highlighted in [35]. Of course at the moment of its introduction the IGCT required a more complicated production costs. Actually the IGCT can be considered very simple because of the development of the makers. This device is affirmed on the market also for its availability because there are not many things that fail its [35]. Moreover about its junction aspects the IGCT is not sensitive to dv/dt and di/dt problems [35].

I.2.4

CSC-Phase controlled converters

CSCs are the most affirmed structures in the field of HVDC systems [19]. The basic converter is depicted in Figure I-36, this is a classical 6-pulse topology.

Figure I-36: Rectifier bridge based on phase-controlled thyristors

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Typical voltage waveforms are presented in Figure I-37. The DC waveform depends on the line-to-line AC voltages. The average value on the DC voltage (2) can be fixed by controlling the turn-on angle of the semiconductor devices respect to the line-to-line voltage.

Vuv

Vvw

Vwu

-Vuv

-Vvw

-Vwu

Vo

150 100 50 0 -50

ψ

-100 -150 0.044

0.046

0.048 Time (s)

0.05

0.052

Figure I-37: Line to line voltage waveforms for the 6-pulse converter

The relationship between the turn-on angle and the amplitude of the DC voltage imposed by this system is described in Figure I-38.

v1 = V 2.sin(ω0t)

(1) 3 6

π

3 < VOUT1 >= V 6. cosψ

π

(2)



V

ψ(°)

Rectifier

0

30

60

90

120

150

180

Inverter



3 6

π

V

Figure I-38: DC voltage regulation according to the phase angle

The turn-on angle ψ determines also the phase between the current and the line-neutral voltage. A typical current waveform of a 6-pulse thyristor converter is depicted in Figure I-39. At high current level, the inductance on the ac-side l cannot be ignored. In fact for a given angle ψ, the current commutation takes a significant commutation interval δ which influences also the maximum negative limit on the DC voltage [36]. 17

Chapter I

HVDC Systems

100 v1

[p.u.]

50

+I

0

i1

0

-50

δ

-I ψ

-100 0

0.002

0.004

0.006

0.008 0.01 Time [s]

0.012

0.014

0.016

Figure I-39: Typical input current waveform for a 6-pulse rectifier compared with the AC phase voltage

The AC current waveform can be decomposed in a Fourier series (3). The fundamental component shows a phase shift respect to the phase voltage. This means that the regulation of the DC voltage determines the active (4) and reactive power (5) transmission. ∞ 2 3 ⎡ 1 ⎤ I .⎢ sin( ω .t −ψ ) + ∑ . sin[( 6 h ± 1 )( ω .t −ψ )] ⎥ π h =1 6 h ± 1 ⎣ ⎦ 3 6 3 6 (4) P= V .I . cos ψ Q= V .I . sin ψ π π

i1 =

(3) (5)

The typical spectral content is shown in Figure I-40. Nevertheless, it is well known that the harmonic spectrum can be improved by interleaving thyristor commutations with multiwinding transformers to achieve 12-pulse or 24-pulse rectifiers [36]-[37].

2 3

π

.I

1

5 7

11 13

17 19

…………

Figure I-40: Harmonic content for a 6 pulse thyristor rectifier

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The presence of the AC line inductor limits the voltage capability of the converter depending on the line current as (6).

3 3 < vOUT >= V 6. cosψ − l.ω.I

π

(6)

π

The output characteristic of the converter is given in Figure I-41. The curves are marked for different values of ψ. For values ψ greater than 90°, the system works in inverter mode (4th quadrant). In this case there is an extinction time interval, tinv, during which the voltage across the thyristor is negative and beyond which it becomes positive. Time interval tinv should be greater than the thyristor minimum turn-off time tq. Otherwise, the thyristor will prematurely turn-on, leading to a loss on the current control which can be destructive.

3

π

V 6



ψ= 0°

I 0



3

π

tinv

V 6 ψ= 180° Figure I-41: DC voltage capability vs AC current

The current drawn by the power station has to be filtered by LC shunt circuits tuned on the typical frequencies of the low rank harmonics [38]. These filters take-up 20-30 % of the surface employed for the substation which is not negligible. As example, Figure I-42 shows the “field” of LC filters associated to the AC/DC converter station of the France-England connection (2 GW).

19

Chapter I

H HVDC System ms

Figurre I-42: LC shu unt filters at « Les L Madarins » converter station in France - England Inteerconnection

I.2.5

CSC C-HVDC C SYSTEM MS

In this ssection is sh hown the op perating prin nciple for th he converters which chharacterize the t CSC-HVDC link. The basic conneection is com mposed by a voltage rectifier whichh provides the t on line throu ugh the DC current imp position. Thhe regulation n is power neceessary to thee transmissio achieved th hrough the phase p angle ψ1.

ref vOUT 1

Figure I-43: Basic HVDC cconnection bassed on CSC systems

By conssidering the reference cu urrent the co onverter wh hich is in recctifier modee works on the t red charactteristic in Figure F I-44. The T operatin ng power diiagram is sh hown in Figuure I-45 and d it is importan nt to note thaat the contro ol of the actiive power afffects the inp put reactive power. 20

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

Q

Carachteristic of 1

Inverter Characteristic of 2

Rectifier

tinv limit

0

ψ

DC current iref



3 6

π

V .I

Figure I-44: I-V diagram for the two converters

0

3 6

π

V .I

P

Figure I-45: PQ diagram

The converter which gets the power and works in inverter mode is depicted in Figure I-46. The converter must regulate the voltage phase angle ψ2 to operate at the minimum turn-off time tinv and then limit the reactive power received. As shown in Figure I-44, the operating point is given by the intersection of characteristics for the first converter (in red) and the receiver converter (in blue).

ref vOUT 2

Figure I-46: thyristor converter in inverter operation

To change the direction of the power flow it is necessary that the two converters switch the roles. This means an inversion of the DC voltage polarities.

I.2.6

VSC-PWM based AC/DC converters

In this section, after a brief review on the VSC SPWM converters the principles of the HVDC transmission are explained. The so-called Voltage Source Converter based on the Sinusoidal Pulse Width Modulation allows the AC/DC conversion (and vice-versa) by regulating the active and the reactive power independently. The basic structure for the

21

Chapter I

HVDC Systems

conversion is shown in Figure I-47. If the AC voltage is imposed the power flow is regulated via duty cycle α which determines the sign of the current.

Figure I-47: basic structure for the AC/DC conversion based on VSC systems

The basic control diagram for a 3-phase VSC is depicted in Figure I-48. A generator synchronized on the grid voltage vs determines the AC current reference which is composed by active and reactive components. The duty cycle α determines the voltage vr which draw the desired AC current via inductor L [39].

id i L

vs

Vd

vr

n

g1 PI

PLL

α

g6 PWM

ref ireactive i1actref

Figure I-48: Diagram of the control for a VSC PWM converter

According to the duty cycle variation the pulse width modulation is determined as shown in Figure I-49. The phase voltage waveform imposed by the three phase converter on the AC side reaches values between -2/3Vd and +2/3Vd [37]. The fundamental component can reach maximum amplitude equal to Vd/2.

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[p.u.]

1

Pulses α

0.5

0

0.044

0.046

0.048

0.05

0.052 Time [s]

0.054

0.056

0.058

0.06

0.058

0.06

vr

Vd α − 1) (1+α(2)/2*V d 2

0.044

0.046

0.048

0.05

0.052 Time [s]

0.054

0.056

Figure I-49: switch pulses and duty cycle; phase voltage imposed by the converter and its fundamental component waveform

Inductor L determines the current waveform according to the single phase equivalent circuit in Figure I-50.

I

XL ΔV

ACgrid

Vs

Vr

VSC voltage

Figure I-50: Single phase Equivalent circuit VSC-HVDC connection

Amplitude and phase ϕ of the current depends on the active and reactive powers provided to the grid. (Figure I-51).

23

Chapter I

HVDC Systems

100

i v1

[p.u.]

50 0 -50

φ -100

0.044

0.046

0.048

0.05

0.052 Time [s]

0.054

0.056

0.058

0.06

Figure I-51: AC current and grid voltage

As it is shown in Figure I-52, the line current waveform shows a spectrum which has interharmonics centered on the multiple of the switching frequency [40] h is the ratio between switching frequency and fundamental frequency).

1.5

Current [p.u.]

1

(h-2).f (h+2).f 0.5

(2h-1).f (2h+1).f

0

f

hf

3hf

Figure I-52: AC current harmonic spectrum for a PWM VSC structure

Due to the unidirectional DC voltage, the direction of the power flow regulated on the AC side leads on the DC side to a change on the sign of the current averaged value. An example of positive averaged value of the DC current is shown in Figure I-53. Each converter imposes the desired DC voltage through the averaged value of the DC current.

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60

[p.u.]

40

20

0 0.044

0.046

0.048

0.05

0.052 Time [s]

0.054

0.056

0.058

0.06

Figure I-53: id current

Regarding the single phase equivalent circuit at the fundamental frequency (Figure I-50), the corresponding vector diagram converter is given in Figure I-54. The DC voltage determines the output voltage limit of the converter as marked on black ring while the AC current the limit (red ring) is fixed by the semiconductor devices. Then the area corresponding to the intersection of the two rings gives the operative range of the DC/AC converter. According to the references made in Figure I-50 the sign of the power flow is also determined.

P Converter Voltage Limit

Vr

γ ϕ

I react

Vs

jXL I Q

Iact

I RMS Current Limit Figure I-54: Fresnel diagram for a AC/DC VSC structure

25

Chapter I

HVDC Systems

The synchronous reference frame is tuned on the voltage grid v1. By varying the amplitude and the phase γ of Vr the vector jXLI is placed to achieve the desired active (7) and reactive (8) power.

P=3

VS Vr sin γ XL

(7)

Q = 3V S

V r cos γ − V S XL

(8)

In the next section the principle of control to achieve the power sharing is provided for the HVDC link based on VSC structures.

I.2.7

VSC-HVDC systems

The basic lay out of a VSC-HVDC link is highlighted in Figure I-55. The approach supposes that the power is transferred from the source 1 (on the left) to the source 2 (on the right).

vs1

vs2

i1

i1 L

vs1

vr1

id1

≈≈ i v =

+ -

PI ref ireactive

i1act

id2

Vd

i2

v ≈ =

i2

≈ vr2 i =

L

vs2

α2

α1

PLL

P

ref

PI ref ireactive

i2actref

PI

Vdref Figure I-55: simple control strategy for a VSC based HVDC connection

The two terminals share the same voltage on the DC link. The receiver converter (right) draw the currents in grid2 which fixes the active power level. To balance the DC voltage, the converter 1 absorbs the required active power on grid 1. The reactive power controls on each 26

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side are completely independent. The stability of the DC voltage is ensured by the first converter. The DC voltage control generates the reference for the active part of the current necessary to keep the required DC voltage. According to the claims made up to this point, VSC-HVDC systems can be chosen rather than CSC-HVDC ones because of a series of factors, such as: •

Failures of the commutations due to AC network disturbances that could be avoided.



Independent managing of the active and reactive power.



The use of modulations such as PWM, which guarantees frequency very low harmonic distortion on the currents. The AC filter size can be greatly reduced.

That is why in the following section, multilevel VSC topologies, able to operate in high voltage applications, are considered.

I.3 VSC-HVDC multilevel topologies Due to the limited current capability of the cables and semiconductor devices, HVDC systems require converters able to operate on around a hundred volts. In Figure I-56, the main topologies of voltage source inverters are reminded.

Figure I-56: Basic schema of VSC topologies for a simple one a), 2-VSI b), and a multilevel topology c)

The simplest VSC topology is the two-level, three-phase bridge [40]. If this solution is adopted, many series-connected IGBTs are used to compose one device as shown in Figure I-57. As treated previously there is just one manufacturer available on the market for this solution.

27

Chapter I

HVDC Systems

VDC

A

B C

Figure I-57: VSI 2-level topology for high voltage employment

The connection of series devices leads to output voltage waveforms, which show high dv/dt, which is a main constraint for transmission line transformers. Moreover, for highpower converters, the switching frequency is very low due to power losses and the limitations of the semiconductor device. To keep the harmonic impact under the limit imposed by the standards, an AC filter is necessary. The use of multilevel converters enables work at a high-voltage level, with a high-waveform quality. The main feature of these converters is that they draw a quasi-sinusoidal voltage waveform from several levels obtained from flying capacitors (like flying cap converters) [42] connected to each commutation cell. In multilevel structures, due to the interleaved modulation technique, it is possible to achieve a series of advantages [42] - [43], such as: •

Quasi-sinusoidal AC voltage waveform



Low harmonic impact



Reduced costs for the filtering elements



Possible direct connection to the MV grid



Reduction of semiconductor losses due to a very low single-switching frequency per device

An overview is given in the next section on the multilevel topologies candidate to be employed for high-power transmission.

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I.3.1

MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

Neutral Point Clamped (NPC)

One of the topologies which literature started to consider is the NPC [43]. In Figure I-58, a three-level version is shown, but it is possible to add the components and place them correctly to increase the number of levels.

T1 T2

T3 T4

D1

T1 DC1 T2

D2

D3

T3

DC 2

D4

T4

D1

T1 DC1

T2

D2

D3 D4

T3

DC 2 T4

D1

DC1

C

+VDC

D2

D3 D4

DC 2

−VDC C

Figure I-58: Three-level three-phase NPC topology

The component which characterizes this topology is the diode necessary to clamp the switching voltage to the half level of the DC bus, which is split into three levels by two series of connected bulk capacitors. In this topology, the middle point is also called the neutral point, outlined in Figure I-58 as the ground. By increasing the number of levels, the voltage which the diodes have to sustain rises. If the voltage rating of each diode is kept, more devices are necessary for the whole voltage. For this reason, if the number of voltage levels that the system can impose is N, (N-1)2 diodes are necessary. For high-DC voltages, the system becomes less convenient due to the huge number of diodes.

I.3.2

Flying capacitor

Another multilevel topology which is suitable for high-power applications is the Flying Capacitor structure with N imbricated cells (Figure I-59). The output inductor value is calculated to limit the output current ripple at the equivalent switching frequency. [44] The FC topology includes N-1 flying capacitors, and the operating voltage of each cell is Vd/N [44]. One drawback of this topology is the stored energy in the flying capacitors close to the DC bus (voltage and energy increase with index i). However, it is possible to connect capacitors in the series to sustain high voltage, but it is not certain that the voltage will be equally shared between them.

29

Chapter I

HVDC Systems

Figure I-59: Three-phase flying capacitor converter

The two topologies analyzed present a better reduction in the harmonics. Despite the improvements which they are able to reach, these kinds of multilevel converters present a series of limitations/drawbacks. For this reason, they did not succeed in these HV-application demands [47].

30



Not suitable for the industrial series production (thanks to the modular construction in order to enable scaling to different power and voltage levels, using the same hardware [48])



Unwanted EMI disturbances generated by a very high slope (di/dt) of the arm currents



The DC bulk capacitor stores a huge quantity of energy which leads to damages under faulty conditions



The stored energy of the concentrated DC capacitor at the DC-Bus results in extremely high surge currents and subsequent damage if short circuits at the DC-Bus cannot be excluded



Harmonics on the AC current must always be suppressed

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I.3.3

MODULAR M MULTILEVE EL CONVERT TERS FOR H HVDC POWER R STATIONS S

Casca aded Mulltilevel In nverters

These stru uctures are characterized c d by a seriess connection n of elementtary convertters that aree no ormally ideentical, as shown s in F Figure I-60. Each celll correspondds to a vo oltage level.. A According to the particullar modulattion techniqu ue, it is posssible to achiieve the desired voltagee w waveform acccording to th he imposed rreference (F Figure I-61).

Figure I-60: I Cascaded d multilevel stagge Figure F I-61: Ex xample of multtilevel waveforrm

With respeect to the tra aditional toppologies, cascaded strucctures ensurre the modu ularity of thee syystem by en nsuring seriees industrial production n. Due to th he modularitty, they do not presentt up pper-DC voltage limits.. In fact, it is possible to t add more e series cellss to sustain the desired d vo oltage. A topologgy which has h been afffirmed in the last de ecade is thhe Modularr Multilevell Co onverter. Th his structuree is more and d more often n chosen forr VSC-HVD DC power sta ations [45]. The conveerter is a co omposition of series-co onnected ele ementary ceells (Figure I-62). Thiss co onverter offeers the possiibility to reggulate the active and re eactive poweer independ dently. Each h ph hase is comp posed by tw wo groups o of elementarry cells (1..N N and N+1… …2N), calleed branches.. Eaach branch conducts the half-phasee current. Ass affirmed in n [47], “At ffirst glance, when beingg co ompared to convention nal VSC or m multilevel VSC, V the ne ew topologyy offers seveeral featuress w which may seeem strangee or definitelly wrong”. Thanks T to a series of addvantages liisted above,, th he next chap pter pays atteention to thee main topollogy and siz zing aspects for this structure:

31

Chapter I

HVDC Systems



Each arm conducts half current and in continuous conduction mode



Arm inductances contribute to limit faulty conditions



The bulk capacitor is not necessary because there are two terminal cells



Each capacitor cell voltage can be controlled very slowly with respect to the current regulator



The DC link voltage can be controlled by the converter

Figure I-62 : Modular Multilevel Converter base schema

I.4 Conclusions The development of semiconductor turn-off devices and the success of the multilevel topologies in recent years have made VSC-HVDC structures the most employed in HVDC systems. CSC structures can manage high voltages because are composed by thyristor rectifiers. This device does not suffer the series connection. On the other hand, VSC structures can control the active and reactive power independently. Moreover the SPWM based structures make the filtering stage very small respect to the CSC. VSC structures allow also islanded operation. Compared to the traditional multilevel structures, Cascaded multilevel converters, due to their modularity, are matched to series industrial production. Moreover they do not present upper-DC voltage limits. In fact, it is possible to add more series cells to sustain the desired voltage.

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

Chapter II. MMC systems

In the first part of this chapter a macro model is provided for the MMC structure. The socalled averaged model facilitates considerations and investigations without taking into account the effects of the harmonics at the switching frequency, making the study fast and direct. Sizing parameters are provided for the reactive elements (branch inductors and cell capacitors) for two different approaches. A first approach supposes a current control, which acts directly on the AC output current (one current control per phase). Under this condition, a new configuration is also proposed for the branch inductor in order to improve the system performances. The second approach proposes two current loops per phase, each of which acts on the current of each inductor. For both approaches, simulations are performed to validate the study. The considered structure in the work is depicted in Figure II-1. Each phase of the system is composed by two branches. Each branch is a connected series of N elementary cells (EC) and the branch inductor L. Each phase contains 2N elementary cells. At the top are the negative branches (n), and at the bottom are the positive ones (p).

Vd 2

Vd 2

v nu

v nv

v nw

i nu

i nv

i nw

i pu

i pv

i pw

v pu

v pv

v pw

Figure II-1: Modular Multilevel Converter in three-phase configuration

33

Chapter II

MMC Systems

II.1 The Macro Model To make preliminary considerations and gain an easier understanding of the system, a model at low frequency was extracted. A Sinusoidal Pulse Width Modulation (SPWM) is assumed. This approach does not consider the switching contribution on the spectral content for the voltages and currents of the system. Moreover, this approach makes the study of the MMC structure independent from the particularly topology of the series connected elementary converters.

iC(t) io (t ) ⋅ α (t )

vC (t) ⋅α(t)

iC(t) io (t )

vo (t )

io (t ) ⋅ f (t ) ioav (t )

vC (t ) ⋅ f (t )

voav (t )

Figure II-2: Low-frequency model b) of an elementary switching cell a)

Each commutation cell can be seen as a 2-port device (Figure II-2 a)). The input side is characterized by the voltage and current for the cell capacitor. The output side carries out the voltage cell and the branch inductor. The relations between currents and voltages of the cell are at (1) and (10), respectively, where f(t) is the modulation function, depending on the modulation signal and the topology of the elementary converter. Thus, the averaged model of the cell is depicted in Figure II-2 b).

iC (t ) = ioav (t ) ⋅ f (t )

(9)

vo (t ) = vCav (t ) ⋅ f (t )

(10)

By starting from the diagram given in Figure II-1, it is possible to extract the equivalent averaged circuit (Figure II-3) valid for the MMC system; the equations which characterize the structure don’t consider the particularly topology of the elementary converter. Moreover each capacitor resumes the total capacitance for the N converters which compose the branch. The equivalent value is C/N.

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS Id av V cun

av V cvn

C/N

av vnu

fnu Vd/2

av V cwn

C/N

av nv

v fnv

av nu

invav

L

L

i

N

i uav vu

L

av V cvp

C/N

v fpu

av pu

av inw L

i vav vv

i wav vw

L

av i pv

av i pu av V cup

av vnw

fnw

L

Vd/2

C/N

av i pw

n

av V cwp

C/N

v av pv

v av pw

C/N

fpv

fpw

Figure II-3: Averaged model for the MMC

To make the study not-dependent from the particular topology, definitions on the nomenclature about the functions has to be given in Table II-1.

Table II-1: Elementary converters function definition

f(t) k(t) α(t)

Function which multiplied for the averaged cell gain gives the averaged voltage waveform of the cell output AC part of f(t) Averaged value of the switching function. (for a unipolar elementary converter f(t)=α(t); for a bipolar elementary converter α(t)=(1±f(t))/2)

All of the considerations were made just for one phase. Each branch imposes a voltage (11) which is the equivalent sum of the output voltage of each series’ connected cell. Moreover each cell imposes a voltage depending on the modulation function and the voltage capacitor. By supposing the voltages on the capacitors for all the cells of the branch equal between them and the same for all the modulation functions, each branch imposes the voltage in (12) According to the diagram shown in Figure II-3, the phase voltage is achieved in by neglecting the voltage drop on the branch inductor L (13). Branch currents determine the current in the phases (14).

35

Chapter II

MMC Systems N

av vnu (t ) = ∑ V juav (t ) j =1 N

v (t ) = ∑ V (t ) av pu

j =1

av ju

;V juav (t ) = f j (t )Vcjav

(11)

⎧⎪ v = V ⋅ f n (t ) ⎨ ⎪⎩v = V ⋅ f p (t ) av v av (t ) − vnu (t ) vu (t ) = pu 2 av nu av pu

av Cn av Cp

(12) (13)

iu (t ) = inu (t ) − i pu (t )

(14)

The instantaneous and averaged voltage waveforms are compared in the next section. This facilitates better understanding of the difference between the two models.

II.1.1

Macro model validation

The typical voltages and currents of an MMC system are considered to demonstrate the reliability of the macro model. The simulation results are reported in p.u., because the particular case study is shown after the sizing considerations achieved in the next sections. The switching frequency for the single cell is 450 Hz for the instantaneous model. The voltage and currents of the instantaneous model are compared to the averaged ones. Moreover, considerations for the spectral content are achieved to show the frequency limits of the model with respect to the instantaneous one. In Figure II-4, a typical voltage waveform of the capacitor of the elementary converter is shown. The instantaneous model seems to match well with the averaged one. This is consolidated also by the spectral content comparison in Figure II-5.

Capacitor Voltage [p.u.]

1.04 1.02 1 0.98 0.96 0.94 0.92 1.9

Instantaneous Model Averaged model 1.92

1.94

time [s]

1.96

1.98

2

Figure II-4: Instantaneous and averaged model comparison of a voltage on a cell capacitor

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

Averaged [p.u.]

Instantaneous [p.u.]

1 0.8 0.6 0.4 0.2 0 0

50

100 Frequency (Hz)

150

200

Figure II-5: Spectral content comparison of a capacitor voltage for a cell

A more evident matching between the two models is shown by considering the output voltage of the elementary cell (10) in Figure II-6. In this case, the matching between the two models is more evident in their low-frequency spectral content compared in Figure II-7. The averaged model is not able to take into account the switching frequency. 1.2

Instantaneous Averaged

Voltage [p.u.]

1 0.8 0.6 0.4 0.2 0 -0.2 1.9

1.91

1.92

1.93

1.94

1.95 time [s]

1.96

1.97

1.98

1.99

2

Figure II-6: output voltage imposed by an elementary cell; comparison between instantaneous model and averaged model

37

Chapter II

MMC Systems Instantaneous [p.u.]

Averaged [p.u.]

0.5 0.4 0.3 0.2 0.1 0 0

50

100

150

Frequency (Hz)

²

Figure II-7: Spectral content comparison for the output cell voltage

The macro model is very useful in making all preliminary considerations about the reactive element sizing and testing the control. The model implementation is very direct, and the simulations are very fast because the switching frequency is not considered for the time step choice. By now, if it is not specified, all the simulations are performed by considering the averaged model. Before the sizing approach proposition, the elementary cell topology is defined in the next section. The single cell characterizes the MMC base structure [49] by considering a SPWM. A more detailed study on the choice of the cell topology is achieved in chapter III. In this chapter the study in given for the averaged model if the adaptation of the instantaneous one is not specified.

II.1.2

Study of the MMC basic structure

The basic version of the MMC structure is composed by single cells (Figure II-8). The modulation signal given in (15) considers ω0 to be the fundamental frequency and cos(φ) the power factor. Negative and positive branches have duty cycle (16) and (17), complementary between them.

Vd 2

k (t ) = M sin( ω 0 t + ϕ ) ; 0 < M < 1

(15)

1 − k (t ) fn = αn = 2

(16)

f p = α p = 1 − f n (t )

Figure II-8: Simple cell adopted for the MMC structure

38

(17)

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

From the assumptions given for the elementary cells in (1) and (10) and based on consideration for the modulation ratio assumed for the single cell, the branch voltages and currents for the u-phase are carried out in (18) and (19), the positive part is symmetrical to the negative one. The presence of a second harmonic component is confirmed in the works [50][14] and is highlighted as follows.

V2 f ⎧ 1 ⎪⎪vun (t ) = 2 Vd (1 − M sin(ω0t − ϕ )) + 2 sin(2ω0t − ϕ ) ⎨ V ⎪vup (t ) = 1 Vd (1 + M sin(ω0t − ϕ )) + 2 f sin(2ω0t − ϕ ) ⎪⎩ 2 2 I1 ⎧ ⎪iun (t ) = I 0 + 2 sin(ω0t ) + I 2 f cos(2ω0t − ϕ ) I I0 = d ⎨ I 3 ⎪i pn (t ) = I 0 − 1 sin(ω0t ) + I 2 f cos(2ω0t − ϕ ) 2 ⎩

(18)

(19)

Each branch current is composed of three terms:

Vd 2

Vd 2

Id 3



The DC component, which follows the flow shown in Figure II-9 a)



The AC component at the fundamental frequency; according to the flow depicted in Figure II-9 b), each branch conducts half of the phase output current



The second harmonic component, which is kept in the branches (Figure II-9 c)) and represents the energy balance between the negative and the positive branch for each phase [49]-[14]. Moreover, this component doesn’t flow on the DC side because it is a negative sequence.

Id 3

Id 3

iu 2

iv 2

iw 2

iu 2

iv 2

iw 2

iu2

nd

iv2

nd

i w2

nd

Figure II-9: Current flow in the MMC structure

The study of the system was conducted by making two different assumptions according to the considered control approach to the AC current. The two cases are described below:

39

Chapter II

MMC Systems

• The output AC current imposition permits control of the system by considering the AC output current iu. In this case, it is not possible to regulate the branch currents composed also by the 2nd harmonic component, which has to be considered in the study (Figure II-10). In this hypothesis, a method for the passive components sizing is given and, upon consideration for a case study, simulations were achieved. • The branch current imposition operates directly on the branch currents inu and ipu and supposes the AC voltage imposed on the AC output side. In this case, it is possible to achieve the AC output current desired and to suppress the second harmonic components (Figure II-11). Sizing parameters are given in the study, and one more time, the simulation results validated the study.

Id

Id Vnu

Vnu Inu

Inu

Vd

Vd Vu

L

iu

L

vCu

PI i

Vd

* u

Vd

Vu

L

iu

L

Ipu

Ipu

* inu

PI

i *pu

PI Vpu

Vpu

Figure II-10: MMC elementary circuit by imposing the AC output current

Figure II-11: MMC elementary by imposing each branch current

II.2 Output current imposition In this section, the circuit presented in Figure II-10 is studied. The sizing parameters were achieved by starting from considerations made in (18) and (19). Evaluations gave the dependence of voltages and currents on the branch inductors and cell capacitors. By suppressing the current source (Figure II-10), the amplitudes of the 2nd harmonic components of the branch voltages and currents are reported in (20) [49].

I 2 f (t ) = −

40

V2 f 4ω0 L

sin(2ω0t +

π 2

− ϕ ) = I 2 f cos(2ω0t − ϕ )

(20)

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

The capacitor current ic(t) is

1 icn (t ) = iun (t ) ⋅ (1 − M sin(ω0 t − ϕ )) 2 icn (t ) =

I0 I0M I MI − sin(ω 0 t − ϕ ) + 1 sin(ω 0 t ) − 1 sin(ω 0 t − ϕ ) sin(ω 0 t ) + 2 2 4 4 I2 f MI 2 f + cos(2ω 0 t − ϕ ) − cos(2ω 0 t − ϕ ) sin(ω 0 t − ϕ ) 2 2

By using the Werner formulas:

icn (t ) =

I0 I0M I MI MI sin(ω 0 t − ϕ ) + 1 sin(ω 0 t ) − 1 cos(ϕ ) + 1 cos(2ω0 t − ϕ ) + − 2 2 4 8 8 I2 f MI 2 f MI 2 f + cos(2ω 0 t − ϕ ) − sin(3ω 0 t − 2ϕ ) + sin(ω 0 t ) 2 4 4

The current capacitor has also a third harmonic component thus, the capacitor current is achieved in (22) according to (21).

icn (t ) = icn (t ) 0 + icn (t )1st + icn (t ) 2 nd

icn (t ) 0 = icn (t )1st =

(21)

I 0 MI1 − cos(ϕ ) 2 8

1 (I1 − 2 I 0 M cos(ϕ ) + I 2 f M )sin(ω0t ) + I 0 M sin(ϕ ) cos(ω0t ) 4 2 1 icn (t ) 2 nd = ( MI1 + 4 I 2 f ) cos(2ω0t − ϕ ) 8 MI 2 f icn (t ) 3rd = sin(3ω0t − 2ϕ ) 4

(22)

The fundamental current component is sufficient to generate the second harmonic component. Moreover, according to (23), to keep a constant DC component of the capacitor voltage, the DC component of the capacitor current has to be equal to zero, so it is possible to achieve a relationship between the I1 and I0 in (24). It is possible to verify that the amplitude of the third harmonic for the capacitor voltage can be neglected with respect to the other ones. Thus the capacitor voltage (25) and the total branch voltage (26)-(27) can be obtained.

41

Chapter II

MMC Systems

Vd 1 + icn (t )dt N C∫ MI I 0 = 1 cos(ϕ ) 4

Vcn (t ) =

(23) (24)

Vd N 2 ⎤ ⎞ 1 I1 M 1 1⎡ ⎛ M2 cos(ϕ) sin(ϕ) ⋅ sin(ω0t ) − cos2 (ϕ) ⎟⎟ + I 2 f M ⎥ ⋅ cos(ω0t ) Vcn (t )1st = ⎢I1 ⎜⎜1 − 2 ω0C 8 ω0C 4 ⎣ ⎝ ⎠ ⎦ 1 1 (MI1 + 4I 2 f ) sin(2ω0t − ϕ) Vcn (t ) 2nd = 2ω0C 8

(25)

1 − M sin(ωt − ϕ ) ⎤ ⎡ Vun = N ⎢Vcn (t ) ⋅ ⎥ 2 ⎦ ⎣

(26)

Vcn (t ) 0 =

Vd NM ⎡ I2 f M 2 − 3M 2 cos2 (ϕ) ⎤ − + I 1 ⎢ ⎥ sin(ϕ) 2 8ω0C ⎣ 2 4 ⎦ ⎫ ⎧ ⎡ I1MNcos(ϕ)sin(ϕ) Vd cos(ϕ) ⎤ − M⎢ ⎪ ⎪ ⎥ sin(ω0t) + 16ω0C 2 ⎦ ⎪ ⎪ ⎣ Vun(t)1st = ⎨ ⎬ 2 2 ⎡ ⎤ ϕ ( 4 ) 1 4 cos ( ) MN I + MI + − I M I M ϕ sin( ) MV 2f 1 2f 1 ⎪+ ⎢ d cos(ω0t)⎪ − −N ⎥ ⎪ ⎪ ⎢ 2 64ω0C 8ω0C ⎥⎦ ⎭ ⎩ ⎣ I1M 3 N cos(ϕ)sin(ϕ) 2 − M 2 cos2 (ϕ) ⎤ N ⎡ 4I2 f + I1M + M(MI2 f + I1 )⎥ sin(2ω0t −ϕ) + cos(2ω0t −ϕ) Vun(t)2nd = ⎢ 16ω0C ⎣ 2 2 8ω0C ⎦ Vun(t)0 =

(

)

(27)

By fixing the apparent power of the system, Vd and therefore N, I1, and M and varying the power factor, the variation of the amplitude of Vun(t)2nd is not very sensitive to its second term, so it is possible to rewrite Vun(t)2nd as (28). The amplitude of the 2nd harmonic component of the current is therefore extracted in (29).

Vun ( t )2nd = I2 f 2ωL

I 2 f ≈ I1

with

Vun ( t )2nd ≈

M 3 N cos 2 (ϕ ) − 3MN 2 NM 2 − 64 LC ω 2 + 4 N

N ⎡ 4I 2 f + I1 M 2 − M 2 cos2 ( ϕ ) ⎤ + M ( MI2 f + I1 )⎥ ⎢ 16ω0C ⎣ 2 2 ⎦ (28)

(29)

This study permits evaluation of the 2nd harmonic amplitude of the branch currents and voltages from the knowledge of the power rate of the system, Vd and therefore N, I1, and M.

II.2.1

Cell capacitor

The value of the capacitor is extracted according to the ripple amplitude of the voltage at low frequency. By considering equation (25), the components of the voltage do not depend 42

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

only on the capacitor value but also on the I2f , whose extraction is in (29). The evaluation of the capacitor becomes a non-linear problem. For this reason, the evaluation of the cell capacitor was achieved by implementing the formulas given previously in an iterative procedure shown in the flow chart in Figure II-12.

Figure II-12: Iteration method for the capacitor evaluation

II.2.2

Branch inductor

When the second harmonic component in the current is considered, it is necessary to define a limit range within which the branch inductor has to be defined. The inferior limit is given by the ripple amplitude of the branch current due to the commutations of the devices. By assuming a sinusoidal pulse width modulation and considering that all of the cells are interleaved between them, the maximum amplitude of the branch current ripple is ΔIMAX. In (30) is reported the inferior limit of the inductor.

L>

Vd 8 N f c ΔI MAX 2

(30)

The second harmonic component of the branch current contributes to increase the total rms value. If this component is considered, an oversizing of semiconductor devices and the copper of the inductor must be taking into account. According to (29), to limit the amplitude of the

43

Chapter II

MMC Systems

second harmonic component of the branch current, it is necessary to increase the value of the inductor. If the inductor value is significant, its voltage drop at the fundamental frequency could become very great. Usually, the voltage drop on the inductor, ΔVL , has to be kept under a small percentage of the AC voltage to ensure the controllability of the system at network frequency (31).

L<2

ΔVLMAX ω 0 I1

(31)

II.2.2.1 Considerations The only way to limit the branch second harmonic both for the voltage and the current is to size the reactive elements as big as possible. For the current controller, it is not possible to operate on this component, which flows only in the branch (look the grey loop in Figure II-9). The dynamic response of the equivalent internal current loop has to be studied. To extract the equivalent capacitor of each branch the relationship between the output voltage of the vun/p (32) and the branch current iu(n/p) (33) of the averaged branch shown in Figure II-3, if the averaged duty cycle of the cell is considered equal to ½. The branch capacitance is extracted in (38) and for the phase is (39).

C dvCu 1 (t ) = iun (t ) N dt 2 4C dvun (t ) = iun (t ) N dt

(32)

vCu = 2 ⋅ vun

(34)

Ceq =

(33)

4C 2N

(35)

The equivalent circuit of the loop depicted in Figure II-10 is achieved in Figure II-13 for the small signal approximation.

H ( jω) =

Figure II-13: Equivalent RLC circuit of a single phase

44

jωCe q I = 2 V 1 − ω LCeq + jωReqCeq

(36)

ωr =

1 LeqCeq

(37)

ξ=

R C eq 2 Leq

(38)

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

The RLC circuit includes the capacitor, which represents the equivalent capacitance in the phase; then there are the negative and the positive inductors and the resistance, which resumes the dissipative part of the semiconductors and the copper losses. The system is studied like a typical second-order circuit of which the transfer function is (36). According to the particular application, it is possible to achieve some consideration for the bode diagram of the magnitude (Figure II-14), particularly about the frequency resonance (37) and the damping factor (38). If the considered system has to sustain high voltages, the number of cell capacitors N can be considered huge. If the typical value of the cell capacitor is around mF [51], the Ceq is relatively small. Thus, in most cases the frequency resonance fr is greater than the fundamental frequency. Moreover, the branch inductor is around mH if the second harmonic has to be attenuated [50]. This leads to a dumping factor (38) smaller than 1. For these reasons, the fundamental frequency of the system is placed in the positive slope of the magnitude curve (Figure II-14). This means a further increase for the amplitudes of greater harmonics.

0 -20

db [p.u.]

-40 20 0 -20 -40 1

f

2f

fres 20f Frequency [p.u.]

Figure II-14: Bode diagram of a RLC circuit for a typical high voltage system

With these considerations, for this control approach the inductor sizing has to respect the condition on the resonant pulsation given in (38).

45

Chapter II

ωr =

MMC Systems

1 < ω0 LeqCeq

(39)

This condition requires an increment of the mathematical product on the denominator. The chance to increment the value of the capacitor is greatly reduced because of the physical size of this element which is included on each elementary converter. It is not possible to further increment the branch inductor because of the voltage drop condition (31) at the fundamental frequency. For these reasons, in the next section is given a new configuration of the inductor which can better manage the two contrasting conditions given until now.

II.2.2.2 Coupled inductors The aim of this configuration is to achieve an inductor which offers a small series impedance to respect the condition (31) and a high impedance at 2.fr to meet the condition (39). Considerations start from the classical configuration of the 4-port model of a transformer depicted in Figure II-15. The equations which characterize the real transformer are shown in (40).

Figure II-15: 2-port model of a transformer

V1 = [ jω(LT + LM ) + RT ]⋅ I1 + jωLM I 2

V2 = jωLM I1 + [ jω(LT + LM ) + RT ]⋅ I 2

(40)

If the transformer is connected in the configuration depicted in Figure II-16, it can be considered a tripolar component of which equations are reported in (41) and (42).

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

Figure II-16: transformer model in tripolar configuration

V = V1 + V2 I = I1 + I 2

(41)

⎧ R = 2 RT ⇒ V = ( R + jωL ) I ⎨ ⎩ L = 2 LT + 4 LM

(42)

The reactive element provides results that can be considered a simple connected inductor series element for which the schema is shown in Figure II-17. This circuit has a series inductor which has four times the magnetization inductance LM and output impedance LT, which typically is very low as described in (43).

⎧ R = 2 RT ⇒ V = ( R + jωL) I ⎨ ⎩ L = 2 LT + 4 LM

(43)

Figure II-17: Equivalent tripolar element of the coupled transformer

The coupled transformer requires more complicated building costs; on the other hand it presents an equivalent branch inductance which is four times that of the classical version. This can be achieved if the magnetization inductance is sized with the same number of turns of the simple branch inductor. 47

Chapter II

II.2.3

MMC Systems

Simulations

After the choice of the system power rate, in this section, simulations performed validated the sizing parameters given above. Moreover, the improvements through the coupled reactor are shown. A HVDC link to connect an off-shore wind farm platform is considered as a case study. The nominal power level is 100 MW, with a DC voltage of 160 kV. The MMC is rated considering press-packed IGBT. The study is carried out by considering a classical PWM control with an interleaving of the cells. All of the simulations are performed by considering the macro model. The reference structure is depicted in Figure II-3, and it considers just six averaged cells (one per branch), each of which resumes the N interleaved instantaneous cells. Each capacitor corresponds to the whole capacitance of each branch and has to sustain the DC voltage Vd.

II.2.3.1 MMC system with classical branch inductor The main parameters of the system are given in Table II-2.

IDC VDC 2 Table II-2: system power rate

VDC 2

System Power Rate Nominal power Phase to phase Grid voltage Vll Vd Number of sub-modules Voltage capacitor Inductor resistance RS

100 MW 83 kV 160 kV N=64 2.5 kV 60 mΩ

Figure II-18: Case study system

In this case, an inductor equal to 50mH was chosen, and a cell capacitor of 7mF is picked to achieve a voltage ripple around the 10%. According to condition (39), a resonance frequency of 34 Hz was chosen. In Figure II-19, the capacitor voltages are reported only for a single phase. The chosen capacitor keeps the ripple amplitude under the imposed value. 48

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2600

Cell Voltage [V]

VCun/N 2550

VCup/N

2500 2450 2400 1.945

1.95

1.955

1.96 1.965 Time [s]

1.97

1.975

1.98

Figure II-19: Cell voltage normalized on the number of cells

The currents flowing (Figure II-20) in the branch inductors have a limited second harmonic component around 10%, as shown in Figure II-21. Moreover, other harmonics are not amplified, so condition (39) is met.

Current [A]

1000

iun ivn

500

iwn

0

-500 1.95

1.955

1.96

1.965

1.97

1.975 time [s]

1.98

1.985

1.99

1.995

Current [A]

1000

2

iup ivp

500

iwp

0

-500 1.95

1.955

1.96

1.965

1.97

1.975 time [s]

1.98

1.985

1.99

1.995

2

Figure II-20: branch currents

49

Chapter II

MMC Systems

100 Current %

80 60 40 20 0

0

50

100 150 Frequency [Hz]

200

250

Figure II-21: Spectral content of the branch current in percentage with respect to the fundamental component

The huge inductor value makes the system unable to meet condition (31). Figure II-22 reports a huge voltage drop on the inductor, which could cause the system to lose the current controllability. Under these assumptions, the system is not able to quite match all of the conditions imposed in the previous section.

10

ΔV% [V]

8 6 4 2 0 0

100

200 300 frequency [Hz]

400

500

Figure II-22: Percentage spectral content of the voltage drop on the branch inductor

In the next paragraph, the interphase transformer is employed for the MMC structure. This reactor is called to replace the traditional branch inductor to overcome the contrasting conditions given before.

II.2.3.2 Coupled transformer for MMC structure The interphase transformer is chosen with a magnetization inductor LM of 25 mH. The inductor LT candidate to define the series voltage drop VL at the fundamental frequency is chosen to be 20 times smaller than the previous one. A cell capacitor of 6mF is proposed always to achieve a voltage ripple around the 10% mark. By considering condition (39), the resonance frequency of the circuit is 36 Hz.

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Vd 2

Table II-3: Reactive elements sizing

Cell Capacitor LT @ ∆IMAX LM

6 mF 2.5 H 25 mH

Vd 2

Figure II-23: MMC phase with coupled inductors

Figure II-24 reports the capacitor voltages. The chosen capacitor keeps the ripple amplitude under the imposed values.

2650

VCun/N

Voltage [V]

2600

VCup/N

2550 2500 2450 2400 2350 2.95

2.96

2.97 2.98 frequency [Hz]

2.99

3

Figure II-24: Cell voltage normalized on the number of cells

Also, in this case, the branch inductors (Figure II-25) are able to limit the second harmonic component as shown in Figure II-21. Moreover, other harmonics are not amplified so that condition (39) is met.

51

Chapter II

MMC Systems

Current [A]

1000

iun

500

ivn iwn

0 -500 2.95

2.955

2.96

2.965

2.97

2.975 2.98 time [s]

2.985

2.99

2.995

Current [A]

1000

iup

500

ivp iwp

0 -500 2.95

3

2.955

2.96

2.965

2.97

2.975 2.98 time [s]

2.985

2.99

2.995

3

Figure II-25: Branch currents

100 Current %

80 60 40 20 0

0

50

100 150 Frequency [Hz]

200

250

Figure II-26: Spectral content of the branch current in percentage with respect to the fundamental component

The employment of coupled inductors (interphase transformer) better manages the tradeoff between the frequency response condition affirmed in (39) and a low-voltage drop on the series inductor LT depicted by (31). Figure II-27 reports the voltage drop with respect to the phase voltage amplitude provided for the classical branch inductor employment and the coupled inductors employment. The amplitude of the voltage drop is reduced about ten times that of the classical version.

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Traditional Inductor Coupled Tripolar Inductor

10

ΔV % L

8 6 4 2 0 0

50

100 150 Frequency [Hz]

200

250

Figure II-27: Comparison of the harmonic content of the voltage drop on the traditional branch inductor of the previous case and the series inductor LT

For MMC structures, the use of the coupled transformer better manages the hard trade-off between the controllability of the system and the dynamic response. If this approach is adopted, the interphase transformer employment is suggested. In this application, only one current control loop is necessary with respect for other traditional approaches. On the other hand, more complex hardware is necessary.

II.3 Branch current imposition For this approach, there are two controls per phase that operate directly on the branch currents inu and ipu , and the AC voltage is imposed on the AC output side. In this case, it is possible to achieve the AC output current desired and to suppress the second harmonic components (Figure II-11). A detailed description of the control is proposed in Chapter IV. Thus, the voltages v(n/p)u (44)-(45) and the currents i(n/p)u (46)-(47) are reported without the second harmonic component. As evaluated in (21) the current has a DC component which is related to the fundamental one to keep constant the voltage capacitor in the cell. A clearer understanding on the components of the branch currents can be achieved by looking Figure II-9.

u nu (t ) = u u (t ) =

Vd (1 − m(t )); u pu (t ) = Vd (1 + m(t )) 2 2

u pu (t ) − unu (t ) 2

=

Vd m (t ); 2

(44)

(45)

53

Chapter II

MMC Systems

MI1 I cos(ϕ ) + 1 sin(ω0 t ) 4 2 MI I i pu (t ) = 1 cos(ϕ ) − 1 sin(ω0t ) 4 2

(46)

iu (t ) = inu (t ) − i pu (t ) = I1 sin(ω 0 t )

(47)

inu (t ) =

II.3.1

Sizing

The value of capacitor C is chosen to limit the voltage ripple at the fundamental frequency ∆VC provided by (25) and with a neglected second harmonic component. The maximum ripple amplitude is achieved in a pure reactive operating mode, when sin(φ)=1. So the capacitor evaluation in this case is a linear problem and can be extracted from (48)..

C=

I1 V ;VC = d 2ω0 ΔVC N

(48)

II.3.1.1 Considerations on the arm inductor For systems with high power and high voltage, the number of sub modules employed becomes very large. For this reason, the equivalent switching frequency is very high if interleaved modulations are implemented. This allows a very low switching frequency fsw for each device, which leads to a significant reduction in the switching losses. At this condition, the branch inductor value, which is calculated from (30), is very low for a huge number of cells. The second harmonic suppression in the branch is not considered, because it is automatically managed by the current control loop. Problems due to the dynamic response no longer exist because the control approach is different. On the other hand, the branch inductor plays a key role in the limitation of short circuit currents under faulty conditions. For this reason, a low branch inductor means huge short circuit currents. If a branch current control approach is considered, the choice of this reactive element is achieved in order to limit the short circuit current. This aspect is taken into account in V.II. For a limited number of sub modules, usually the branch inductor value given by (30) succeeds in managing a limited short circuit current, too.

II.3.2

Simulations

According to the considerations provided previously, an inductor equal to 10 mH was chosen, the ripple amplitude of the current is kept around 7% (Figure II-28). Only in this case instantaneous model is considered to achieve the current ripple. A cell capacitor of 6mF is considered to achieve a voltage ripple around 10% of the DC value (Vd/N). Simulations are 54

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performed by considering the averaged model shown in Figure II-3. The capacitor voltages reported in Figure II-29 just for a single phase show that the amplitude of the voltage ripple is kept under the imposed value.

Figure II-28: Current ripple on the phase current from the instantaneous model

2600

VCnu/N VCpu/N

Voltage [V]

2550

2500

2450

2400 1.5

1.51

1.52

1.53

1.54

1.55 1.56 Time [s]

1.57

1.58

1.59

1.6

Figure II-29: Voltage capacitor normalized on the number of cells

55

Chapter II

MMC Systems

The currents flowing in the branch inductors (Figure II-30) can be considered sinusoidal. The second harmonic component is reduced and can be considered negligible with respect to the fundamental.

Current [A]

1000

iun

500

ivn iwn

0 -500 1.5

1.52

1.54

time [s]

1.56

1.58

Current [A]

1000

iup

500

ivp iwp

0 -500 1.5

1.6

1.52

1.54

time [s]

1.56

1.58

1.6

Figure II-30: Branch currents

The second harmonic component is greatly reduced if compared to the previous case (output current imposition) as shown in Figure II-31. The current control loop in the branch directly limits the component.

500

Single Output Current Loop Branch current loops

Current [A]

400 300 200 100 0 0

50

frequency [Hz]

100

Figure II-31: Comparison of the branch current -harmonic content

56

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II.4 Conclusions The macro-model makes the preliminary evaluations direct and allows for very fast simulations. The control of the AC output current can lead to a huge second harmonic of the fundamental component in the branch current and an amplification of the greater harmonics. The simple approach of the control has to be compensated by hardware which becomes more complicated and expensive. On the other hand, the second approach facilitates the employment of more simple hardware. Of course, it requires a slightly more complicated control that is not a problem today thanks to the large choice of control devices available on the market. For these reasons, the second control approach was chosen herein the thesis.

57

Chapter II

58

MMC Systems

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Chapter III. New multilevel topologies

A topological study is consolidated and extended in this chapter on three different cell topologies. The study of each cell is achieved, and their employment for the MMC structure is treated. For each cell, topology advantages and limits are discussed in terms of current and voltage. By fixing the nominal power of the system and the DC link voltage, the cells are studied and compared in terms of current and voltage on the AC output. It is shown that also improvements on the rating of the reactive elements can be achieved if other topologies are chosen as the elementary cell with respect for the basic cell employed. An analytic approach for the power losses evaluation is given. The losses in the semiconductor devices are evaluated for each topology. In the second part of this chapter a new multilevel structure is presented. For each phase this topology adopts just one branch and interfaces itself with the grid through the zig-zag transformer. The new structure is compared with the MMC one in terms of sizing. Moreover the so-called multilevel Half wave structure is proposed in order to upgrade the old three phase rectifiers based on diodes/thyristors. The upgrating is achieved by keeping the same grid transformer and therefore the voltage and current levels. Simulations are performed in order to validate the study and evaluate the advantages.

59

Chapter III

III.1

New multilevel topologies

Elementary converters for the MMC Structure

The choice of the elementary converter depends on the current and voltage which the MMC system has to conduct and to impose. A series of preliminary considerations on the power flow and the control approach are necessary to determine the voltage and current waveforms. As it was introduced in the previous chapter, the branch current control approach is chosen. For VSC-HVDC systems, as discussed in the chapter I, the grid voltage is imposed so the power flow is regulated through the current regulation as shown in the base circuit reported in Figure III-1. The basic control for an MMC structure is depicted in Figure III-2 according to the choice made in previous section. To simplify the representation, only one phase is depicted; the considered phase voltage and current are shown in (49)-(50). The averaged model is considered for the analysis, and the controlled sources (vnu and vpu) resume the N series connected converters.

i nuref

Figure III-1: AC side of the DC-AC transmission

iu = 2I sin(ω0t )

(49)

vu = 2V sin(ω0t − ϕ )

(50)

ref i pu

Figure III-2: Current regulation for the power flow provided for a MMC structure

Considerations regarding voltages and currents are given by splitting the circuit in the AC and DC part (principle of superposition). The study is performed only for one phase. According to the AC circuit of the MMC structure (Figure III-3), the branch currents (51) and voltages (53) are provided. This is valid if the branch inductors have the same value and a negligible voltage drop. For the DC part of the system (Figure III-4), each branch conducts the third part of the DC current (52) because of the three phases. The controlled voltage source in the branch must balance the DC link voltage according to (54).

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Id

vnuAC i nuAC

VnuDC InuDC

Vd 2 ≈0

Vd 2

AC i pu

AC v pu

Figure III-3: AC circuit of the MMC structure

⎧ AC iu ⎪ inu = 2 ⎨ i AC ⎪i pu =− u 2 ⎩ ⎧⎪vnuAC ≈ − vu ⎨ AC ⎪⎩ v pu ≈ vu

(51)

(53)

DC I pu

VpuDC

Figure III-4: DC circuit of the MMC structure

⎧ DC I d ⎪ I nu = 3 ⎨ I DC ⎪ I pu = d 3 ⎩ ⎧ DC Vd ⎪Vnu = 2 ⎨ V ⎪V puDC = d 2 ⎩

(52)

(54)

To balance the AC and the DC sides, each branch must conduct the currents in (55) and impose the voltages in (56).

iu I d ⎧ ⎪ inu = 2 + 3 ⎨ i I ⎪i pu = − u + d 2 3 ⎩

(55)

Vd ⎧ ⎪vnu = −vu + 2 ⎨ V ⎪ v pu = vu + d 2 ⎩

(56)

The active and the reactive power on the AC side are reported in (57).

PAC = 3VI cos(ϕ ) Q = 3VI sin(ϕ )

(57)

On the DC side the active power is achieved in (58).

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Chapter III

New multilevel topologies

PDC = Vd I d

(58)

From a power balance between the DC and AC side the (59) is carried out.

Vd I d = 3VI cos(ϕ )

(59)

In the next three sections, different topologies for the elementary converters are presented as candidates to be employed for MMC structures. Limits and advantages are highlighted for each topology. The approach supposes that each branch voltage is the equivalent sum of the N series converters as depicted in the previous section. The averaged model was considered for the study to make the analysis fast and direct. Moreover, a sinusoidal pulse width modulation is supposed.

III.1.1 Single Cell This is the base cell topology used for MMC structures. This cell presents two transistors with anti-parallel diodes (Figure III-5). This topology allows the imposition of a monopolar voltage and the conducting of a bi-directional current. The study is provided for the negative part of the system; considerations on the positive part are directly deducted for symmetry.



Monopolar voltage



Bi-directional current

Figure III-5: Single cell topology

This structure can impose only a positive voltage as shown in Figure III-6. If the considered branch voltage is (56), the condition (60) must be met. The voltage on the cell capacitor VC must make the system able to reach all the voltage levels required as depicted by (61).

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vun N.VC

V 2

Vd 2

V 2≤

Vd 2

N ⋅ VC = 2.

0

t

(60)

Vd 2

(61)

Figure III-6: Averaged voltage waveform if the single cell is considered

So the modulation signal is reported in (62) if the value of M is considered maximum 1.

) 2 2V 2 2V k (t ) = sin(ω 0 t − ϕ ) , M = Vd Vd

(62)

The power balance in (59) is considered between the AC and the DC side to carry out the current waveform. The relationship between the AC and the DC currents is performed if the AC voltage amplitude in (62) is considered. The current waveform is shown in Figure III-7 by employing the single cell for an MMC structure.

Id

0 I d 3

iun I 2 2

Id 3

t

3 I d = M 2I cos(ϕ ) 4

(63)

Figure III-7: Averaged current waveform if the single cell is considered

This balance is also necessary to ensure a constant dc voltage across the capacitor. The right power balance also indicates a constant voltage capacitor in the cell and therefore the right energy balance in the branch.

63

Chapter III

New multilevel topologies

III.1.2 Asymmetrical H-bridge This topology guarantees the bipolar voltage, but it can only conduct a unidirectional current. The considered circuit is shown in Figure III-8.



Bi-polar voltage



Monodirectional current

Figure III-8: Asymmetrical H-bridge topology

For this topology, the branch current has to be kept as expressed in (64). This condition leads to a balance between the AC and DC components of the currents carried out in (65).

iun

2 Id 3

I 2 2

0

Id 3

iun (t ) =

t

Id 2 + I sin(ω0t + ϕ ) ≥ 0 3 2

3 I 2 ≤ Id 2

(64) (65)

Figure III-9: Averaged current waveform if Asymmetrical H-converter is considered

The choice of a current with a high DC component increases the rms value. This means an oversizing of the semiconductor devices. To optimize the semiconductor choice, the balance (65) is chosen so that the DC component is equal to the AC one. Under this condition, by substituting (65) in the power balance (60), the relationship between the AC and DC voltages is achieved in (66). This means that the use of the asymmetrical HB-topology is not suggested for reactive power compensations because of the high DC link voltage levels required. Then, the following study was performed only with the unit power factor.

V Vˆ = d cosϕ 64

(66)

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

The voltages imposed by each branch are expressed by (67) where N is the number of elementary converters per branch. The total number of elementary converters has to be chosen according to (68) where f is the modulation signal.

V vun (t ) = N ⋅ Vˆ ju = d − Vd sin(ω 0t ) 2 Vd ˆ vup (t ) = N ⋅ V ju = + Vd sin(ω 0 t ) 2 ) V ⎛1 ⎞ f (t )n = d ⎜ − sin(ω0t ) ⎟ Vd NVC ⎝ 2 ⎠ , M = V ⎛1 ⎞ N ⋅VC fˆ (t ) p = d ⎜ + sin(ω0t ) ⎟ NVC ⎝ 2 ⎠

(67)

(68)

To ensure a linear SPWM modulation the peak value of f(t) has to be less than 1. The ratio between the number of elementary converters and the DC voltage is carried out in (69).

vun 3.Vd 2

0

N.VC

V 2

Vd 2 Vd 2 -N.VC



t

3 N ⋅ VC ≥ Vd , 2

(69)

Figure III-10: Averaged voltage waveform if asymmetrical H-bridge topology

In this case, the voltage level NVC , which enables the system to reach the maximum amplitude of the branch voltage, is 1.5 times that of the DC voltage. This means a 50% increase for the number of elementary converters per branch with respect to the employment of the simple cell. On the other hand, considerations on the sizing capacitor make this topology more attractive.

III.1.2.1 The capacitor of the Asymmetrical H topology and the AC current The voltage imposed by the Asymmetrical H-topology is double that of the simple one. By fixing the values of the DC voltage and the system power rate, the active power is provided for the single elementary converter (70) and for the asymmetrical H bridge topology (71). In the comparison between the two powers in (72), it is shown that, if the asymmetrical H bridge 65

Chapter III

New multilevel topologies

topology is employed, half of the current is necessary to achieve the same power, also decreased by M.

PAC = PAC

3

M SC ⋅Vd ⋅ I SC 2 2 3 = Vd ⋅ I AH 2

(70) (71)

The amplitude of the voltage ripple on the capacitors depends on the AC current (48). Thus, to achieve the same amplitude of voltage ripple, at parity of capacitor voltage of the elementary converter, less than half of the capacitance is necessary in terms of single cell use (72).

I AH = M SC

I SC C → C AH = M SC SC 2 2

(72)

III.1.3 H-bridge The so-called four-quadrant converter can manage the bi-directional propriety in the current of the single cell, and it can impose a bi-polar voltage as the asymmetrical H-bridge topology. On the other hand, the H-bridge topology requires double the components of the others, four transistors and four diodes, as depicted in Figure III-11.

T4

T1

D4

D1

iun VC

Vju T3

D3

T2



Bi-polar voltage



Bi-directional current

D2

Figure III-11: H-bridge topology

In (73) the voltage condition to respect is reported. The equivalent sum of the output voltages waveform is highlighted in Figure III-12.

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Vd
(73)

vun

N.VC

3.Vd 2

V 2

0

Id

Vd 2 Vd 2 -N.VC



t

Figure III-12: Averaged output voltage of the Hbridge converter

iun

0 I d 3

I 2 2

Id 3

t

Figure III-13: Averaged current waveform in the Hbridge converter

In (74), the current condition’s waveform is highlighted in Figure III-12.

I 2 2 Id ≤ . 2 3 cos ϕ

(74)

Under ordinary operative conditions, the H-bridge structure is not necessary for the MMC systems. On the other hand, if this cell is configured like a single cell, the bi-polarity can be used in the case of DC fault, which is addressed in the chapter V.

III.2

Efficiency for multilevel structure

Regarding the power level, 1% of losses is not negligible (1 GW correspond to 10 MW of losses). For this reason many semiconductor producers consider efficiency as an ‘alternative fuel’. Thus, the power losses evaluation is not a secondary problem. The monitoring of the losses becomes more attractive for high-voltage applications when the number of devices is very high. In this chapter, the modular multilevel structure is studied in terms of efficiency. An investigation on the power losses in semiconductor devices is carried out by taking into account the previously described cells. An analytical approach was given for each case. After fixing the nominal power and the DC voltage for the converter, the efficiency of the system is evaluated for each kind of employed cell. The analytical results are validated by simulations performed by PSIM software.

67

Chapter III

New multilevel topologies

III.2.1 The analytical approach A three-phase balanced operation is assumed and then only one elementary converter is considered. The current in the devices should be carefully determined and the definition of the conduction intervals is fundamental to evaluate conduction and switching losses [52]-[55]. Conduction losses (76) are evaluated by considering a piece-wise linear approximation of the forward characteristic (75) r0 is on state resistance and V0 the voltage threshold) [56]. Averaged and RMS values are calculated according to expressions (77) and (78) where α is the duty cycle of the control signal. Assuming θ=ω0t, θ2-θ1 is the conduction angle of the devices.

VT / D = rT / D 0 I C + VT / D 0

(

(75)

)

2

(76)

i (t )α (t ) dθ

(77)

rms PTcond + VT / D 0 ITavg/ D / D = rT / D 0 I T / D

I Davg/ T =

I Trms = 1

1 2π

θ2

∫θ

1

1 2π

θ2

∫θ

i (t ) 2 α (t ) d θ

(78)

1

For the calculation of the switching losses, we considered, for the energy curves given by the manufacturer datasheets, a second order approximation [56]. Coefficients adev, bdev and cdev in (79) come from this approximation. PTsw/ D =

f sw 2π

∫θ (a θ2 1

dev

) VV

⋅ i 2 (t ) + bdev ⋅ i (t ) + c dev ⋅

i

ref



(79)

Conduction and switching losses extracted in this section suppose a commutation frequency much higher than the fundamental frequency [56].

III.2.2

System rating

In Table III-1 the nominal power and the devices are defined. Moreover from the semiconductor datasheet the linear coefficients of the conduction curve and the coefficients of second order of the energy curve are shown. The number of cells, AC output current and voltages are extracted according to the cell topology chosen for the system.

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POWER CONVERTER S = 100 MVA DC voltage Vd Cell voltage Switching frequency fsw = 200 Hz

160 kV 2.5 kV

IGBT COEFFICIENTS @ VCC=2.8 kV TRANSISTOR TOSHIBA“S6X06B” rT0=1.3mΩ; VT0=1.5 V aon+aoff=-15n; bon+boff=12.1m; con+coff=-2.4m

DIODE EUROPEC “D 1331 SH”

rD0=1.3mΩ; VD0=1.1V arec=-2μ; brec=5.2m crec=0.57

III.2.3 Single cell& Full H-Bridge The performed study is valid for both the single and for the full H-bridge cell. This last one in ordinary conditions is configured like a single cell. The bipolar voltage is provided only for faulty conditions. The losses of both the switching and conduction depend on the duty cycle and on the current in the device. The RMS and the average values of the current in the devices are carried out in this section.

III.2.3.1 Current calculation As it was shown in Figure III-14, for the study the negative branch is chosen. All capacitor voltages are considered with a constant value VC=Vd/N moreover for the current we consider a waveform without ripple at the switching frequency. For the H-bridge cell (Figure III-15), in normal operation, the device 3 is always on while the device 4 is always off. In terms of power losses, devices 1 and 2 are analyzed according to the analytical method adopted for the simple cell. In normal condition the device 4 is always opened while the device 3 conducts always without commutations.

Always opened T4

D4

T1

D1

VC

iun T3

Figure III-14: Single cell configuration

D3

T2

D2

Always closed Figure III-15: H-bridge configuration

The duty cycle is given by (80). 69

Chapter III

α n (t ) =

New multilevel topologies

1 − k (t ) ; α p (t ) = 1 − α n (t ) 2

(80)

In Figure III-16, the modulation signal f(t) and the current in a cell of the negative branch inu (46) are reported. Due to the current waveforms, the conduction interval of the devices depend on the sign of cos(φ). The DC component of the current determines different losses between the two switches of the cell.

TABLE III-2 – Conduction intervals of the devices

M sin(ωt+φ) ω0 t

Dev.

T1

φ inu(t)

D1 T2

M cos(ϕ ) ) − arcsin( 2

Iu M cos(ϕ ) 4

π + arcsin(

0

ω0t M cos(ϕ ) ) 2

2π − arcsin(

D2

Conduction Interval [θ1 ; θ2] [π+asin(Mcos(φ)/2) ; 2π-asin(Mcos(φ)/2)] [-asin(Mcos(φ)/2); π+asin(Mcos(φ)/2)] [-asin(Mcos(φ)/2); π+asin(Mcos(φ)/2)] [π+asin(Mcos(φ)/2) ; 2π-asin(Mcos(φ)/2)]

Current

Mod. index

iun(t)

αn(t)

iun(t)

αn(t)

iun(t)

αp(t)

iun(t)

αp(t)

M cos(ϕ ) ) 2

Figure III-16: Modulation signal and cell current

TABLE III-2 gives for each device the conduction interval and the associated current. The current averaged values were evaluated by solving integrals (77) and (78) according to TABLE III-2. The results are given in expressions (81), (82) and (83).

= I Davg = I Tavg 1 1

I1 M 2 cos 2 (ϕ ) 4 − M 2 cos 2 (ϕ ) 1 − 16π 4

(

)

(81)

I Tavg 2

⎡ ⎤ M 2 cos 2 (ϕ ) 2 2 + ⎢ 4 + M cos ϕ 1 − ⎥ I1 ⎢ 4 ⎥ = 16π ⎢ ⎛ ⎞⎥ ⎛ M cos(ϕ ) ⎞ ⎢ 2 M cos(ϕ ) ⋅ ⎜⎜ 2 ⋅ a sin ⎜ ⎟ + π ⎟⎟ ⎥ 2 ⎝ ⎠ ⎝ ⎠ ⎦⎥ ⎣⎢

(82)

I Davg2

⎤ ⎡ M 2 cos2 (ϕ ) 2 2 + ⎥ ⎢ 4 + M cos ϕ 1 − I1 ⎢ 4 ⎥ = 16π ⎢ ⎞⎥ ⎛ ⎛ M cos(ϕ ) ⎞ ⎢2M cos(ϕ ) ⋅ ⎜⎜ 2 ⋅ a sin⎜ ⎟ − π ⎟⎟⎥ 2 ⎢⎣ ⎝ ⎠ ⎠⎥⎦ ⎝

(83)

(

(

70

)

)

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

In a similar way, integral (78) allows calculating current RMS value for each device. The results are given from expression (84) to expression (87)

ITrms 1

⎧ ⎛M ⎞ ⎫ 2 2 ⎪6π + 6 M cos ϕ − 12 ⋅ a sin ⎜ 2 cos(ϕ ) ⎟ + ⎪ ⎝ ⎠ ⎪ ⎪ 2 2 ⎪ M cos ϕ ⎪⎪ I 1 ⎪ 3 3 = 1 −⎬ ⎨ 2 M cos ϕ − 2 M cos(ϕ ) ⋅ 1 − 4 12π ⎪ 4 ⎪ 2 2 ⎪ ⎪3M π cos (ϕ ) ⎪ ⎪ ⎭⎪ ⎩⎪

(84)

I Drms 1

⎫ ⎧ ⎛M ⎞ 2 2 ⎪6π − 6 M cos ϕ − 12 ⋅ a sin ⎜ 2 cos(ϕ ) ⎟ − ⎪ ⎝ ⎠ ⎪ ⎪ M 2 cos 2 ϕ ⎪⎪ I1 1 ⎪⎪ 3 3 −⎬ = ⎨ 2 M cos ϕ − 2 M cos(ϕ ) ⋅ 1 − 4 4 12π ⎪ ⎪ ⎪ ⎪3M 2π cos 2 (ϕ ) ⎪ ⎪ ⎪⎭ ⎪⎩

(85)

ITrms 2

⎫ ⎧ ⎛M ⎞ 2 2 ⎪6π + 12 + 18M cos ϕ ⋅ a sin⎜ 2 cos(ϕ ) ⎟ + ⎪ ⎝ ⎠ ⎪ ⎪ I1 M 2 cos2 ϕ ⎪⎪ 1 ⎪⎪ 3 3 = +⎬ ⎨ 2M cos ϕ + 34M cos(ϕ ) ⋅ 1 − 4 12π ⎪ 4 ⎪ 2 2 ⎪ ⎪9 M π cos (ϕ ) ⎪ ⎪ ⎪⎭ ⎪⎩

(86)

I Drms 2

⎧ ⎛M ⎞ ⎫ 2 2 ⎪6π − 12 + 18M cos (ϕ ) ⋅ a sin⎜ 2 cos(ϕ ) ⎟ − ⎪ ⎝ ⎠ ⎪ ⎪ I1 M 2 cos 2 ϕ ⎪⎪ 1 ⎪⎪ 3 3 = +⎬ ⎨ 34M cos(ϕ ) + 2 M cos ϕ ⋅ 1 − 4 12π ⎪ 4 ⎪ ⎪ ⎪9M 2π cos 2 (ϕ ) ⎪ ⎪ ⎭⎪ ⎩⎪

(87)

(

)

(

)

(

)

(

)

(

)

(

)

(

g1 =

)

(

1 2π

)

ϕ

⎛ M cos ⎞ ⎟ ⎟ 2 ⎠ ⎝ ⎛ M cos ϕ ⎞ ⎟ − a sin ⎜⎜ ⎟ 2 ⎠ ⎝

π + a sin ⎜⎜



(a

dev

) VV

⋅ i 2 (t ) + bdev ⋅ i(t ) + c dev ⋅

C

dθ =

ref

⎤ ⎡ ⎛ ⎞ M ⎜ 2π − 4 + 2 M 2 cos 2 ϕ ⋅ a sin ⎛⎜ cos(ϕ ) ⎞⎟ − ⎟ ⎥ ⎢ 2 ⎝ 2 ⎠ ⎟ ⎥ ⎢ a I1 ⎜ ⎟+ ⎥ ⎢ dev 16 ⎜ 2 2 cos M ϕ ⎜ ⎟ 2 2 ⎥ ⎢ 6 cos( ) 1 cos ( ) M M ϕ π ϕ ⋅ − + ⎜ ⎟ ⎥ ⎢ 4 ⎝ ⎠ ⎥ ⎢ ⎞ ⎥V ⎢ I1 ⎛⎜ M 2 cos 2 ϕ ⎛M ⎞ 2 M cos(ϕ ) ⋅ a sin ⎜ cos(ϕ ) ⎟ + 4 1 − − Mπ cos(ϕ ) ⎟ + ⎥ C = ⎢bdev ⎜ ⎟ Vref 4 2 4 ⎝ ⎠ ⎢ ⎝ ⎠ ⎥ ⎥ ⎢ ⎥ ⎢c ⎛⎜ π − 2 ⋅ a sin ⎛⎜ M cos(ϕ ) ⎞⎟ ⎞⎟ ⎟ ⎥ ⎢ dev ⎜ 2 ⎝ ⎠⎠ ⎥ ⎢ ⎝ ⎥ ⎢ ⎥ ⎢ ⎦ ⎣

(

g2 =

1 2π

)

⎛ M cosϕ ⎞ ⎟ 2π − a sin⎜⎜ ⎟ 2 ⎠ ⎝ ⎛ M cosϕ ⎞ ⎟ + a sin⎜⎜ ⎟ 2 ⎠ ⎝

∫π

(a

dev

) VV

⋅ i 2 (t ) + bdev ⋅ i(t ) + cdev ⋅

C

(88)

dθ =

(89)

ref

71

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New multilevel topologies

⎤ ⎡ ⎛ ⎞ M ⎜ 2π + 4 + 2M 2 cos 2 ϕ ⋅ a sin ⎛⎜ cos(ϕ ) ⎞⎟ + ⎟ ⎥ ⎢ 2 ⎝ 2 ⎠ ⎟ ⎥ ⎢ a I1 ⎜ + ⎟ ⎥ ⎢ dev 16 ⎜ 2 2 M cos ϕ ⎜ ⎟ 2 2 ⎥ ⎢ + M π cos (ϕ ) ⎟ ⎜ 6 M cos(ϕ ) ⋅ 1 − ⎥ ⎢ 4 ⎝ ⎠ ⎥ ⎢ ⎞ ⎥V ⎢ I1 ⎛⎜ M 2 cos 2 ϕ ⎛M ⎞ ⎟ + Mπ cos(ϕ ) + ⎥ C ⎢bdev ⎜ 2 M cos(ϕ ) ⋅ a sin ⎜ cos(ϕ ) ⎟ + 4 1 − ⎟ Vref 4⎝ 4 ⎝ 2 ⎠ ⎢ ⎠ ⎥ ⎥ ⎢ ⎛ ⎞ M ⎛ ⎞ ⎥ ⎢c ⎜ π + 2 ⋅ a sin ⎜ cos(ϕ ) ⎟ ⎟ ⎟ ⎥ ⎢ dev ⎜ 2 ⎝ ⎠⎠ ⎥ ⎢ ⎝ ⎥ ⎢ ⎥ ⎢ ⎦ ⎣

(

)

⎧adev = aon + aoff ⎧adev = arec f sw f sw ⎪ ⎪ sw P = g 2 ∧ ⎨ bdev = bon + boff PD1 = g1 ∧ ⎨ bdev = brec 2π 2 π ⎪c = c + c ⎪c = c rec ⎩ dev ⎩ dev on off

(90)

⎧adev = arec ⎧adev = aon + aoff f sw ⎪ f sw sw ⎪ P g = ∧ P = g1 ∧ ⎨ bdev = bon + boff D2 ⎨ bdev = brec 2 2 π 2π ⎪c = c + c ⎪c = c rec ⎩ dev ⎩ dev on off

(91)

sw T1

sw T2

= PTsw 1

⎧adev = aon + aoff ⎧adev = arec f f sw ⎪ ⎪ g 2 ∧ ⎨ bdev = bon + boff PDsw1 = sw g1 ∧ ⎨ bdev = brec 2π 2π ⎪c = c + c ⎪c = c on off rec ⎩ dev ⎩ dev

(92)

= PTsw 2

⎧adev = arec ⎧adev = aon + aoff f sw ⎪ f sw ⎪ sw g 2 ∧ ⎨ bdev = brec g1 ∧ ⎨ bdev = bon + boff PD2 = 2π 2π ⎪c = c + c ⎪c = c rec ⎩ dev ⎩ dev on off

(93)

The unsymmetrical current waveform makes the calculation more complicated compared to a classical Voltage Source Inverter. Knowing the RMS and averaged values of the currents the conduction losses can be easily evaluated considering expression (76). Switching losses are calculated by considering integral (79) and conduction intervals depicted in TABLE III-2. It is possible to define functions g1 and g2 as reported in (88) and (89). Nevertheless, switching losses change according to the sign of cos(φ) as it is shown in expressions (90) to (93).

III.2.3.2 Case study The power losses evaluation was performed in different operating modes: inverter and rectifier at unit power factor and reactive power compensation. By keeping the same semiconductor devices, analytical calculations were validated by PSIM software. According to the analysis of the cell topology, the parameters in TABLE III-3 are extracted to carry out the power required by the system (Table III-1).

Iu [rms] Vll [rms]

αMAX N

693 A 83 kV 0.925 64

TABLE III-3 – system parameters if the single cell or the H-bridge cell are used

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III.2.3.3 Results for Single Cell As it is shown in Figure III-17 and Figure III-18, in the unit power factor operation the MMC presents a strong dispersion of the power losses between the devices as expected from the previous section. In the reactive power compensation, the currents in the branches of the MMC become symmetrical and the losses calculation is then equivalent to a classical VSI, moreover the inductor case is the same of the capacitor case (Figure III-19).

1200 1000

Power [W]

600 400 200 0

Conducting Total Switching

1000

800

800 600 400 200

T1

T2

D1

0

D2

Figure III-17: Cell power losses for MMC in Inverter operating mode

T1

T2

D1

D2

Figure III-18: Cell power losses for MMC in Rectifier operating mode

1200

Conducting Total Switching

1000 Power [W]

Power [W]

1200

Conducting Total Switching

800 600 400 200 0

T1

T2

D1

D2

Figure III-19:Cell power losses for MMC in reactive operating mode

73

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New multilevel topologies

III.2.3.4 Results for the full H-bridge Analytical results are reported in Figure III-20 to Figure III-22. For the switching devices 1 and 2 the power losses evaluation was performed as in the elementary cell. Just conduction losses for S3 are added.

rms

1200

Conducting Total Switching

1000

1200

Conducting Total Switching

1000 Power [W]

800 Power [W]

rms

1400

600 400

800 600 400

200 0

200 T1

T2

T3

D1

D2

0

D3

Figure III-20: Cell power losses for MMC in Inverter operating mode

T1

T2

T3

D1

D2

D3

Figure III-21: Cell power losses for MMC in Rectifier operating mode

rms

800 700

Conducting Total Switching

Power [W]

600 500 400 300 200 100 0

T1

T2

T3

D1

D2

D3

Figure III-22: Cell power losses for MMC in reactive operating mode

The addition of semiconductor devices makes the full H-bridge more expensive in terms of losses. For this reason an investigation on the total losses of this cell respect to the simple cell was carried out. In Figure III-23 and Figure III-24 the increases are shown.

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1.2

Traditional Cell H-Cell

Power %

1 0.8 0.6 0.4 0.2 0

Figure III-23: Increase of the losses for a 3-Phase system by using full H bridge cells respect to a classical system

INV REC IND CAP Figure III-24: Total losses comparison for a 3-phase system by considering the classical cell and the full H bridge cell

III.2.4 Asymmetrical H-Bridge With respect to the previous topologies, the asymmetrical H-Bridge solution shows different current waveforms in semiconductor devices and different modulation ratios. Due to the symmetry, just the negative branch is considered; the reference circuit is reported in Figure III-25. The current has only one direction as in (94). For this reason, diodes D1 and D2 in nominal operating condition are not used. For each pair of devices, in (95) and (96) are reported the modulation ratio necessary for the calculation of RMS and average currents.

iun (t ) =

Iˆ (1 + sin(ω0t )) 2 1⎡

(94) ⎞⎤ ⎠⎦

⎛1 ⎝

α n (t ) = ⎢1 + M ⎜ − sin(ω0t ) ⎟⎥ D3,D4 2 2 ⎣

1⎡

⎛1 ⎝

⎞⎤ ⎠⎦

α n' (t ) = 1 − α n' (t ) = ⎢1 − M ⎜ − sin(ω0t ) ⎟⎥ 2 2 ⎣

Figure III-25: Asymmetrical H-Bridge employed for the negative branch

(95) (96)

T1,T2

III.2.4.1 Current calculation According to (77), the average value of the devices is extracted in (97), while the RMS values are reported in (98) and (99). According to the current direction, shown in Figure III-25, only T1, T2, D3 and D4 are conducting.

75

Chapter III

I Davg/ T =

New multilevel topologies

1 2π



I Drms =

1 2π

I Trms =

1 2π



0

iun (t ) ⋅ α (t )dθ =









0

0

Iˆ 4

(97)

2 (t ) ⋅ α n (t ) d θ = iun

Iˆ 1 ⎛ 3 M ⎞ ⋅⎜ − ⎟ 2 2 ⎝2 4 ⎠

(98)

2 (t ) ⋅ α n' (t ) dθ = iun

Iˆ 1 ⎛ 3 M ⎞ ⋅⎜ + ⎟ 2 2 ⎝2 4 ⎠

(99)

According to (78) the switching losses can be expressed by (100).

⎡ 3 ⎤ V Iˆ PswT / D = f sw ⋅ ⎢a ⋅ Iˆ 2 + b ⋅ + c ⎥ ⋅ C 2 ⎣ 8 ⎦ VCC

(100)

To calculate the total losses, an equivalent case study with same power rating and same DC voltage level was considered (see Table III-1). According to the asymmetrical H-bridge properties, the AC voltage value is increased with respect to a topology using simple cells (66).

III.2.4.2 Results As we said before, the power losses evaluation was performed only for a unit power factor. By keeping the same semiconductor devices and ratings (Table III-1), analytical calculations were validated by PSIM software by making rating adaptations in TABLE III-4 due to this kind of topology.

Iu [rms] Vll [rms]

αMAX

295 A 121 kV 0.925

VC N

2.5 kV 113 TABLE III-4 – System parameters

Losses for this elementary converter are balanced between the components as shown in Figure III-26. Of course the total losses are the double (Figure III-27) respect to the single cells due to the number of elementary converters necessary for the employment of this topology.

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

700 600

Total Losses %

500 Power [W]

1.5

Conducting Total Switching

400 300 200

1

0.5

100 0

T1

T2

D3

D4

Figure III-26: Single elementary converter losses

III.3

0

Asymmetric HB

Simple Cell

Figure III-27: Total losses percentage comparison with the single cell

Conclusions

The MMC structure by Professor R. Marquardt is based on single-cell topologies. This cell cannot impose negative voltages; thus, in the case of DC faults, only the branch inductor can limit the current. The asymmetrical H-bridge topology needs the same number of devices per elementary converter. It can impose a bi-polar voltage that better limits the over-currents in faulty conditions. Moreover, at the parity of power sizing and capacitor voltage, this topology allows a reduced value of the capacitance. On the other hand, the number of elementary converter is around the double rather than the single cell use; moreover, this topology is not suitable for reactive power compensations. Of course this topology can be employed for CSC based applications where the power reversibility is achieved with the DC voltage reversibility. If the four-quadrant operation is required with a good limitation of over-currents, then the use of the H-bridge cell is suggested. Moreover, this cell causes the MMC structure not to depend on the voltage and current levels; this aspect is well consolidated in the next section. Of course, the employment of double the components increases the costs. The power reversibility with this topology can be achieved with both the DC voltage and the DC current. The analytical power losses study makes the evaluation fast and direct. It was not easy to carry out the formulas due to the DC component in the device’s current. If the DC voltage value is maintained, the Asymmetrical H-bridge is not so convenient in terms of power losses, despite the lower RMS AC current. This is because, in the Asymmetrical H-bridge, each device conducts during the whole period. Nevertheless, if this cell is employed, a reduced capacitor value can be achieved. Finally, the 25% increasing losses with respect to the singlecell employment is not acceptable for the HVDC employments which usually require almost 1% of the total losses (including losses in the reactive elements). For many other applications with a relatively reduced power the full H-bridge topology is recommended, because it can be employed like a single cell in ordinary operating conditions, and it can limit the current in faulty operating conditions.

77

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New multilevel topologies

III.4 New Modular Multilevel Half Wave topology with zigzag transformer As shown previously, each branch of the MMC structure has a DC and AC component in the voltage and current. The combination of two branches per phase makes possible the right power transferring of the two components according to the assumptions made in the previous chapter and the circuit diagrams given in Figure III-3 and Figure III-4. The proposed structure requires just the upper part of the MMC structure as shown in Figure III-28. This configuration absorbs on the AC side currents with a DC zero sequence. To avoid the saturation of the magnetic core a secondary winding with a zig-zag configuration is used [57]-[58]. Thanks to this coupling, secondary voltages are balanced while the DC zero sequence current is canceled on the primary side. On each phase, several DC/AC cells (converters) are connected in series. Output currents i’u ,i’v and i’w are imposed by three independent control loops which provide a Pulse Width Modulation to the DC/AC converters (101). The phase voltage is chosen according to (102) i'u =

(101)

Id ˆ I 2 + I cos(ω0t − ϕ ) ; i'v = I d + Iˆ cos(ω0t − ϕ − 2 π ) ; i ' w = d + Iˆ cos(ω 0 t − ϕ + π ) 3 3 3 3 3

v'u (t ) = Vˆ sin(ω0t )

(102)

Id VCu1

≈ = Elementary Converters

VCuN

iu

vu N3

N1

iv iw

N2

vv

v’v

vw

v’w

≈ =

VCv1



vbu VCvN

VCw1

=

≈ =

vbv ≈ =

VCwN

vbw ≈ =

i’u i’v i’w

Vd

v’u v’v v’w

N

n

Figure III-28 – Upgraded AC/DC converter

From Figure III-28 the averaged model presented in Figure III-29 is developed and valid at the fundamental frequency. By neglecting the voltage drop across the leakage inductor of the transformer LS, voltage Vbu can be expressed by (103).

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

fu (t) = mu (t)

Vbu

Vbv

f v (t ) = mv (t )

f w (t ) = mw (t )

Vbw

Vd

Figure III-29 - Simplified circuit on the AC side with averaged model of the Half Wave multilevel converter

V Bu (t ) ≈ V d − Vˆ sin( ω 0 t )

(103)

Each elementary converter has to conduct the third part of the DC current and the AC current necessary to achieve the power required if a unitary transformation ratio is provided for the zig-zag transformer. By considering the same capacitor voltages VC and the same DC current, if Vd is the DC voltage for the traditional structure a fast comparison in terms of sizing can be achieved for the same cell topology (Single Cell). Moreover for the zig-zag transformer a unitary transformation ratio N1/N2 is chosen. The voltage imposed by each branch is evaluated in (108) to keep a unipolar voltage; the modulation signal is so extracted in (109). V Bu (t ) ≈ V d ⋅ (1 − sin(ω 0 t ) )

) f (t ) ⋅ N ⋅ VC = Vd (1 − sin( ω 0 t ) )

(104) (105)

The sizing comparison in Table III-5 highlights that for the modular multilevel Half Wave the double of the cells per phase are necessary respect to the classical MMC. The sources Vbx in

79

Chapter III

New multilevel topologies

fact have to sustain all the DC voltage. Moreover the half of the current is imposed on the AC side because the AC voltage is the double respect to the classical MMC structure.

MMC Number of cells AC rms voltage AC rms current

Vd VC Vd

2.N = 2. V = M.

2 2 P I= 3.V

Multi HW with zig-zag V N = 2. d VC

V = M.

I=

Vd

P 3.V

2

Ratio Multi HW/MMC 1 2 ½

Table III-5: Comparison on the sizing of the classical MMC structure and the Multilevel Active Front End

In many cases the new structure can be used to replace systems where there is a pre-existent zig-zag configuration such as the application chosen as case study in the next section.

III.4.1

3 MMC Half Wave topology to upgrade obsolete diode/thyristor rectifiers In this section a particular association of AC/DC multilevel converters is proposed to update classical 3-pulse diode or thyristor rectifiers. The approach is made by keeping the preexisting transformer and voltage values both on the AC and DC side. The use of 3-pulse diode or thyristor rectifiers can be considered one of the first structures to achieve a AC/DC conversion. In literature, it is well known that the simplicity of this topology leads to a series of drawbacks [59]. Due to current waveforms show on the AC side, these rectifiers present a poor power factor. Due to severe constraints on Power Quality, these kinds of topologies are associated to harmonic filters which increase the complexity of the conversion system [60]. Moreover half wave rectifiers show a DC current component on the three phase currents that influences the transformer rating. At this effect, a transformer with a zigzag coupling can be used [59]. Nowadays, in the frame of Medium and High Power applications, new requirements on power quality lead to draw a quasi-sinusoidal current waveform with a four quadrant operation. For this reason, classical diode/thyristor rectifiers are obsolete and should be replaced. With the view to save money, it is necessary to update the traditional topology by keeping the same transformer and the same output voltage level. Nevertheless, active front end solutions based on multilevel voltage source inverters [61] are not suitable to control the DC voltage in the same conditions as a thyristor rectifier (the average output voltage is always lower than the input voltage).

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III.4.1.1 Three phase half wave rectifier The 3 pulse bridge rectifier presented in Figure III-30 absorbs on the AC side currents with a DC zero sequence as shown in Figure III-31-a [62].To avoid the saturation of the magnetic core a secondary winding with a zig-zag configuration is used [57]-[58]. Thanks to this coupling, secondary voltages are balanced while the DC zero sequence current is canceled on the primary side as it is shown in Figure III-31-b.

Figure III-30: Three phasehalf bridge rectifier with zigzag transformer.

Current [A]

a) i'u i'v

0 0.4

Current [A]

i'w

I_AV 0.41

0.42

0.43 Time [s] b)

0.44

0.45

0.46

iu iv

I_AV=0

0.4

iw

0.41

0.42

0.43 Time [s]

0.44

0.45

0.46

Figure III-31 – AC Current waveforms at secondary side (a) and primary side (b) of the transformer

81

Chapter III

New multilevel topologies

III.4.1.2 The case study In a half wave three phase rectifier, voltages on AC and DC side are respectively defined by expressions (106) and (107) by considering the averaged circuit in Figure III-29. Thus, the upgraded system has to be able to manage the power with the same voltage level. So the branch voltage (108) and the modulation signal (109)-(110) are evaluated.

v'u (t ) = Vˆ sin(ω0t )

(106)

3 3 ˆ V 2

(107)

Vd =

3 3 V Bu (t ) ≈ V d − Vˆ sin( ω 0 t ) with Vd = Vˆ

(108)

⎛3 3 ⎞ fˆ (t ) ⋅ N ⋅ VC = Vˆ ⎜⎜ − sin(ω 0t ) ⎟⎟ ⎝ 2π ⎠

(109)



Vˆ N ⋅ VC

⎛3 3 ⎞ Vˆ ⎜ ⎟ ≤ m (t ) ≤ − 1 ⎜ 2π ⎟ N ⋅ VC ⎝ ⎠

⎛3 3 ⎞ ⎜ ⎟ ⎜ 2π + 1⎟ ⎝ ⎠

(110)

To keep constant the capacitor voltage on each elementary converter, the power level has to be the same on DC and AC side (111). This statement leads to a direct relation between Id and Iˆ (112). Thus, expression (112) shows that the current waveform has positive and negative values requiring a converter topology bidirectional in current.

PDC = PAC

Id =

⎧ PDC = Vd I d ⎪ with ⎨ VˆIˆ = P 3 cos(ϕ ) ⎪⎩ AC 2

π ˆ I cos(ϕ ) 3

(111)

(112)

As discussed in the previous section, the multilevel AC/DC converter has to be based on four quadrants elementary converters as depicted in Figure III-11. Left column of TABLE III-6 shows the main parameters considered for the multilevel converter rating. Considering 4.5 kV IGBTs or IGCTs devices and according to (109).The switching frequency is fixed to 350 Hz and the value of the capacitor is calculated to achieve a voltage ripple under 2%.

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

DC link

POWER CONVERTER SN = 10 MVA

DC Link Voltage (Vd)

10 kV

Transformer secondary voltage V’ll 23 kV

Magnetization Inductance LM Total Leakage Inductance

2.6 kV

DC capacitor voltage VC

Zigzag Transformer

12 H Number of Cells per phase N

10

12.7 mH Cell Capacitor

10 mF

Winding Resistance

0.7Ω Switching Frequency

Turn ratio N1/N2= N1/N3

3.76

350 Hz

TABLE III-6 – Converter Rating

To validate this study a model based on the time-domain simulation tool PSIM was developed. Simulation results are presented below. In Figure III-32-a, the multilevel voltage waveforms imposed by the converters are shown. As it was highlighted in expression (108), the DC offset makes these waveforms unsymmetrical. Figure III-32-b show capacitor voltages and validate the choice of the capacitor value which guarantees a voltage ripple of 2%.

a)

4

Voltage [V]

x 10 2

VCu

1

VCv VCw

0 2.93

2.94

2.95

2.96

4

Voltage [V]

1.5

x 10

2.97

2.98

2.99

3

Vd

1 0.5 2.93

Voltage [V]

Time [s] b)

2.94

2.95

2.96

Time [s] c)

2.97

2.98

2.99

3

2620

Eu1

2600

Ev1

2580

Ew1

2560 2.93

2.94

2.95

2.96

Time [s]

2.97

2.98

2.99

3

Figure III-32: Simulation Results – Voltage waveforms.

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New multilevel topologies

Current [A]

Figure III-33-a show the secondary current waveforms with a DC component. As expected, the primary current waveforms presented in Figure III-33-b are quasi-sinusoidal with a very low harmonic distortion.

800 600 400 200 0 -200 2.9

i'u i'v i'w 2.91

2.92

2.93

2.94

2.95 Time [s]

2.96

2.97

2.98

2.99

Current [A]

500

iu iv

0 -500 2.9

3

iw 2.91

2.92

2.93

2.94

2.95 Time [s]

2.96

2.97

2.98

2.99

3

Figure III-33 – Simulation Results – Current Waveforms

Improvements on the AC side in terms of current are shown in Figure III-34. The single loop topology allows achieve negligible fundamental greater harmonics. This leads to a big reduction of the filtering elements.

400

SingleLoop 3p hb

Current [A]

300

200

100

0

0

100

200

300

400 500 600 Frequency [Hz]

700

800

900

Figure III-34: comparison spectral content of the phase current

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1000

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

Conclusions

In terms of sizing the MMC Half Wave structure is the same respect to the MMC, of course the new topology does not require the branch inductor because it utilizes the leakage inductance of the zig-zag transformer. In a classical MMC structure the transformer has to sustain a DC insulation equal to the half of the DC voltage. This is not the case for the new topology, a classical insulation is sufficient. The multilevel converter proposed to upgrade old rectifiers seems attractive. It draws on the AC side quasi-sinusoidal current waveforms. Furthermore, thanks to the cascaded H Bridge, a four quadrant operation can be achieved on the DC side. Nevertheless, the number of required devices could be very expensive. On the other hand, changing the transformer turns ratio could be a cheaper solution requiring a lower number of semi-conductor devices for the same output voltage.

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Chapter IV. PWM Control for Modular Multilevel Converter

A control strategy for modular multilevel structures is proposed in this chapter. The scenario of the modulations techniques is described considering Phase Shift Modulation PWM. In a classical VSI, the control imposes the desired output currents and keeps a constant voltage on the DC link. For multicellular structures the right balance among the voltages of each elementary converter is necessary, too. For PS-PWM employment, the control for multilevel structure is carried out through three main control loops which are described hereafter. The regulators are defined and synthetized for each control loop. A system of 100 MW composed by 64 elementary converters per branch is considered as a case study for which sizing parameters were provided in the second chapter. Simulations were performed to validate the control strategy by ensuring the right set-up of the regulators. The chosen simulation environment is MATLAB-PSIM.

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IV.1

PWM Control C for Modular M Multitilevel Convert rter

Introd duction n

In the last decade the attentio on of researcch and development fo or modulatio ion techniqu ues have playeed a key ro ole for mulltilevel strucctures [39], [70]-[71]. The goal w was to extend traditional techniques to multilevel cases. Th he control of o multilevell structures requires mo ore d more semiconducctor devices. On the oth her hand, bbenefits can be complex sttrategies to drive derived fro om managin ng multiple degrees off freedom (the availability and reedundancy for f instance). The devvelopment and a the deta ailed descripption of thee main mod dulation techhniques in the t frame of th he multilevell structures are well deffined in [72]]. The diagra am in Figurre IV-1 depicts the scenariio. In this work w the stu udy of mod dulation tech hniques is focused f on Phase Shiftted PWM, deriived from th he extension n to multilevvel structuress of the tradiitional PWM M techniquee.

Figure IV-1: I Scenario of the modulattion techniquees for multileve el structures [722]

The straategy adoptted in this work w for m multi-cell top pologies asssociates eachh carrier to o a particular eelementary converter c orr power cell to be modu ulated indep pendently ussing sinusoid dal PWM respectively. Th he modulatio on provides also an even n power distribution am mong the cellls. arrier phase shift of 360 0◦/N is intro oduced acrooss the cells to For a convverter with N cells, a ca generate th he quasi-sinu usoidal outpu ut waveform m [73].

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Principle of the Phase shifted PWM for MMCs

One more time the averaged model of the structure shown in Figure IV-2 is proposed in order to make the preliminary study fast and direct. The subscript “av” in the formulas is neglected to better visualize the equations. The instantaneous model is used only if specified.

IDC av V cun

av V cvn

C/N

av vnu

C/N

fnu VDC/2

vnvav fnv

av nu

invav

L

L

i

N

i uav vu

L

v av pu fpu

av vnw

av V cvp

vv

i wav

v av pv

n

v av pw

C/N

fpv

vw

L

av i pw av V cwp

C/N

av inw L

i vav

av i pv

av i pu

C/N

C/N

fnw

L

VDC/2

av V cup

av V cwn

fpw

Figure IV-2: Averaged model for a MMC structure

The control for SPWM modulated multilevel structures has to ensure that: •

The system is able to impose the desired current to achieve the required power



In each phase the capacitors are on the desired voltage level

• The voltages among the capacitors of each elementary converter are balanced between them. The unbalancing can be caused by different tolerances of passive components, unequal conduction and switching losses in the semiconductor devices or signal imbalance and resolution issues inherent in the control circuit including voltage/current sensors [63]. For these reasons the control approach needs three controllers which are arranged according to the diagram in Figure IV-3.

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V

VC 1( n / p ) ...VCN ( n / p )

Branch Energy Balancing

I

n/ p Active

Branch Current Control

f1( n / p)

α1( n / p)

f2α adapt * VDC /N

1

Cell Balancing N

α N( n / p ) f N( n / p )

Figure IV-3: SPWM Control approach for a multicellular structure

The energy balancing and the current control follow the classical cascaded disposition of the VSC based structures. The energy balancing provides the required active power, through a current reference, in order to keep the capacitors charged. In ideal conditions where all the cells of the system are equal and balanced, with the same losses and with sensors with the same characteristics, the cell balancing control could be neglected. This control only regulates the voltage of each capacitor around the right level, which is just reached by the energy-balancing controller. Thus this loop adjusts the voltage on the capacitor by directly interfering on the modulation signal. The control approach does not depend from the particular topology of the elementary converter. The scaling between f(t) and the duty cycle α(t) is immediate. Each controller of Figure IV-3 was presented and developed for the MMC structure. Moreover simulations were performed to validate the study on the 100 MW system presented in the previous chapters and recalled in Table II-2. The system was sized according to the considerations carried out in section II.3. For a better understanding the averaged model was considered.

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IDC VDC 2

Table IV-1: system power rate

System Power Rate Nominal power Phase to phase Grid voltage Vll Vd Number of sub-modules Branch inductor L Cell Capacitor C Voltage capacitor Cell switching frequency Inductor resistance RS

VDC 2

100 MW 83 kV 160 kV N=64 10 mH 6 mF 2.5 kV 200 Hz 60 mΩ

Figure IV-4: Case study system

IV.2.1 Current control loop The study supposes that the averaged model of the MMC (shown in Figure IV-2) is connected on the AC side with a balanced (16) and symmetrical three-phase grid (114).

vu (t ) = 2V sin (ω0t ) iu (t ) = 2 I sin (ω0t − ϕ )

2 ⎞ 2 ⎞ ⎛ ⎛ (113 vv (t ) = 2V sin ⎜ ω 0 t − π ⎟ vv (t ) = 2V sin ⎜ ω 0 t + π ⎟ ) 3 3 ⎝ ⎠ ⎝ ⎠ 2 2 ⎞ ⎞ ⎛ ⎛ iv (t ) = 2 I sin ⎜ ω 0 t − π − ϕ ⎟ iw (t ) = 2 I sin ⎜ ω 0 t + π − ϕ ⎟ (114 3 3 ⎠ ⎠ ) ⎝ ⎝

As discussed in the second chapter the superimposition approach facilitates the study and allows for easier understanding. In Figure IV-5 the control strategy for the AC part of the system is depicted. The system supposes that there is not DC current for the symmetry condition. The structure can be seen as two independent STATCOMs (negative and positive).

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v nuAC

v nvAC

i u* 2

i nuAC

i

i u* 2

AC pu

AC i nw

i v* 2

i nvAC

i v* 2

i pvAC

AC v pu

AC v nw

AC i pw

AC v pw

AC v pv

Figure IV-5: Control approach for the AC part for a MMC structure

Each voltage of the branch generator can be regulated to impose the required current through the branch inductor. The AC part of the current for each branch is required to be the half of the phase current. According to the symmetry conditions one of the branch currents per STATCOM depends on the other ones as written in (115).

(

AC inw = − invAC + inuAC

)

(

AC AC i pw = − i pvAC + i pu

)

(115)

This means that for each STATCOM just two branch voltage generators can be controlled according to the simplified schema shown in Figure IV-6 for the negative part and in Figure IV-7 for the positive part.

i(AC u / v) p

i(AC u / v) n

v(AC u / v)n Figure IV-6: Simplified circuit for the negative part of the structure

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v(AC u / v) p Figure IV-7: Simplified circuit for the positive part of the structure

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For each part the equations (116) and (117) are achieved by considering the branch inductors without copper losses.

⎧ d AC AC ⎪ L dt inu (t ) = −(vnu (t ) + vu (t )) ⎨ d ⎪ L invAC (t ) = −(vnvAC (t ) + vv (t )) ⎩ dt

(116)

⎧ d AC AC ⎪ L dt i pu (t ) = −v pu (t ) + vu (t ) ⎨ d AC ⎪ L i pvAC (t ) = −v pv (t ) + vv (t ) ⎩ dt

(117)

In order to control the AC part of the MMC structure it is necessary to respect the four equations independently. The control strategy for the DC part of the structure is shown in the layout in Figure IV-8.

* I DC DC v nu

VDC 2

VDC 2

i nuDC

v nvDC

DC i nw

i nvDC

DC i pw

DC i pv

DC i pu

DC v pu

DC v nw

DC v pv

DC v pw

Figure IV-8: Current control loop for the DC part of the MMC structure

The u and v current controls are supposed to work well. The control must provide just the balance in (118). The current loop in Figure IV-8 is achieved in (120). Since the two controlled generators are driven by the same loop the (120) is developed into (121).

DC DC I DC = iuDC ( n / p) (t ) + iv( n / p) (t ) + iw( n / p) (t ) = iu ( n / p) (t ) + iv( n / p) (t ) + iw( n / p) (t )

(118)

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I DC DC DC = iuDC ( n / p ) (t ) = iv ( n / p ) (t ) = iw( n / p ) (t ) 3 DC DC v wn (t ) + v wp (t ) = VDC − LL

(119)

d 2L d DC DC I DC − I DC ; v wn (t ) = v wp (t ) dt 3 dt

2L ⎞ d ⎛ DC DC 2vwn (t ) = 2vwp (t ) = VDC − ⎜ LL + ⎟ I DC 3 ⎠ dt ⎝

(120) (121)

Finally for the current control, the branch generators have to be driven to comply with the five equations summarized in (116), (117) and (121).

IV.2.2 dq0 reference frame The advantages coming from the control implemented in the dq0 reference frame with respect to the time domain are well known and described in the literature [64], [65]. In this section the control approach represented in the dq0 reference frame is shown and then simulations are performed to validate this study. During the steady state of the system the currents in the branches are thereby extracted in (122) for the negative part and in (123) for the positive part of the system.

I DC ⎧ AC ⎪inu (t ) = inu (t ) + 3 ⎪⎪ I DC AC ⎨inv (t ) = inu (t ) + 3 ⎪ ⎪i (t ) = i AC (t ) + I DC nu ⎪⎩ nw 3

(122)

I DC ⎧ AC ⎪i pu (t ) = i pu (t ) + 3 ⎪⎪ I DC AC ⎨i pv (t ) = i pu (t ) + 3 ⎪ ⎪i (t ) = i AC (t ) + I DC pu ⎪⎩ pw 3

(123)

According to the park transformation the dq0 components are evaluated according to (124) and (125) [66].

⎧ 2 2 ⎤ ⎡ ⎪⎡idn (t ) ⎤ ⎢ sin(ω0t ) + sin(ω0t − 3 π ) + sin(ω0t + 3 π ) ⎥ ⎡inu (t ) ⎤ ⎥ ⎪⎢i (t ) ⎥ 2 ⎢ ⎥ ⎢ ⎨⎢ qn ⎥ = ⎢cos(ω t ) + cos(ω t − 2 π ) + cos(ω t + 2 π )⎥ ⋅ ⎢ inv (t ) ⎥ 0 0 0 ⎪⎣i0 n (t )⎦ 3 ⎢ 3 3 ⎥ ⎢⎣inw (t )⎥⎦ ⎪ 1 / 2 1 / 2 1 / 2 ⎥⎦ ⎢ ⎣ ⎩ ⎧ 2 2 ⎤ ⎡ ⎪⎡ idp (t ) ⎤ ⎢ sin(ω 0 t ) + sin(ω 0 t − 3 π ) + sin(ω 0 t + 3 π ) ⎥ ⎡i pu (t ) ⎤ ⎥ ⎪⎢ i (t ) ⎥ 2 ⎢ ⎥ ⎢ ⎨⎢ qp ⎥ = ⎢cos(ω t ) + cos(ω t − 2 π ) + cos(ω t + 2 π )⎥ ⋅ ⎢ i pv (t ) ⎥ 0 0 0 ⎪⎢i0 p (t )⎥ 3 ⎢ 3 3 ⎥ ⎢⎣i pw (t )⎥⎦ ⎣ ⎦ ⎪ 1/ 2 1/ 2 1/ 2 ⎣⎢ ⎦⎥ ⎩

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The dq0 components of the current for each part (negative and positive) of the MMC are so extracted in (126). Of course, the dq components depend on the AC part of the branch currents because the second part of the sum is equal to zero. To perform the current control loop the dq0 transform of the derivate has to be carried out according to (116), (117) and (121). For this reason the derivate in the time domain for (124) and (125) are achieved in (126). The 0 components are evaluated by considering the (118) and (119)

d AC d d 2 ⎤ 2⎡d 2 i( n / p ) d = ⎢ iuAC iv ( n / p ) sin(ω0t − π ) + iwAC( n / p ) sin(ω0t + π )⎥ + ( n / p ) sin(ω 0 t ) + dt dt dt 3 ⎦ 3 ⎣ dt 3 2⎡ 2 2 ⎤ AC π ) + ω0iwAC( n / p ) cos(ω0t + π )⎥ + ⎢ω0iuAC ( n / p ) cos(ω0 t ) + ω 0 iv ( n / p ) cos(ω0 t − 3⎣ 3 3 ⎦ d 2 ⎡ d AC d AC 2 d AC 2 ⎤ i( n / p ) q = ⎢ iu ( n / p ) sin(ω0t ) + iv ( n / p ) sin(ω0t − π ) + iw( n / p ) sin(ω0t + π )⎥ + dt dt dt 3 ⎣ dt 3 3 ⎦

(126)

2 ⎤ 2⎡ 2 AC π ) + ω0iwAC( n / p ) cos(ω0t + π )⎥ − ⎢ω0ivAC ( n / p ) cos(ω0 t ) + ω 0 iv ( n / p ) cos(ω0 t − 3⎣ 3 3 ⎦ d d d 1⎡d ⎤ 1d i( n / p ) 0 = ⎢ iu ( n / p ) + iv ( n / p ) + iw( n / p ) ⎥ = I DC dt dt dt 3 ⎣ dt ⎦ 3 dt In order to achieve a better visualization, (126) was rearranged in the form of (127) for the negative part of the system and (128) for the positive one.

⎧d ⎡ di nAC ⎪ i nd (t ) = ⎢ ⎪⎪ dt ⎢⎣ dt ⎨ ⎡ di nAC ⎪ d i ( t ) = ⎢ ⎪ dt nq ⎪⎩ ⎣⎢ dt

⎤ ⎥ + ω 0 i nq ⎥⎦ d ⎤ ⎥ − ω 0 i dn ⎦⎥ q

(127)

⎧d ⎡ di pAC ⎪ i pd (t ) = ⎢ ⎪⎪ dt ⎢⎣ dt ⎨ AC ⎪ d i (t ) = ⎡ di p ⎢ ⎪ dt pq ⎢⎣ dt ⎪⎩

⎤ ⎥ + ω 0 i pq ⎥⎦ d ⎤ ⎥ − ω 0 i pd ⎥⎦ q

(128)

The obtained equations show the dependency between the d and q components, as described in [63]-[65]. So the results in (116) and (117) and (121) in the dq0 reference frame become (129) and (130).

⎧ d ⎪ L dt ind (t ) − ω0 Linq = −(vnd (t ) + vd (t )) ⎪⎪ d ⎨ L inq (t ) + ω0 Lind = −(vnq (t ) + vq (t )) ⎪ dt ⎪ ( L + 2 L ) d I (t ) = V − 2v (t ) L DC DC 0 ⎪⎩ 3 dt

(129)

⎧ d ⎪L dt i pd (t ) − ω0 Li pq = −v pd (t ) + vd (t ) ⎪⎪ d ⎨ L i pq (t ) + ω0 Li pd = −v pq (t ) + vq (t ) ⎪ dt ⎪ ( L + 2 L ) d I (t ) = V − 2v (t ) L DC DC 0 3 dt ⎩⎪

(130)

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Evaluations showed that the d and q components of the current are coupled between them [64]. In the next section d and q components are decoupled to simplify the regulator synthesis.

IV.2.2.1 The regulator synthesis In order to test only the current control loop, the system in Figure IV-9, the averaged branch, is considered by substituting the capacitor with a voltage source.

VC(n / p) =

VDC N

i(n/ p) (t) ⋅ f (t)

i(n/ p) (t) VC(n/ p)(t)⋅ f (t)

Figure IV-9: Averaged model of the MMC branch to test the control loop

The PLL adopted is the Feed Forward q-PLL which generates the direct component synchronous reference frame. The chosen q-PLL was consolidated in [68] for its fast and robust latching. As described before the dq current controls are performed for the positive and negative part of the structure. According to (129) and (130) the decoupling layouts are achieved in Figure IV-10 for the negative part and in Figure IV-11 for the positive part.

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Current controller v d Negative part

vu vv vw * i nd

PLL

ω0 t

inu u, v, w inv inw

+ -

PI

i nd

ω 0L

i nq

d , q,0

-

* i nq

+

In0

Plant

vd

Negative part

- v nd +

-

- +

+

ind

1 sL

ω0L

ω 0L

ω0L - vnq +

PI

-

vq

-

-

vq -

i nq

1 sL

Figure IV-10: Layout of the control for the negative part in dq0 reference frame

vu vv vw

i *pd

PLL

i pu

ω0 t

Current controller v d positive part + i pd

i pv u, v, w

i pw

i pq

d , q,0

i *pq I p0

+

PI

vd

+ v pd +

- +

Plant

positive part

+ +

ω0L

i pd

ω0L

ω0L PI

1 sL

ω0L - vpq + -

vq

+

-

vq +

1 sL

i pq

Figure IV-11: Current controller plant in dq0 reference frame for the positive part of the structure

After the decoupling the d and q components can be independently treated as depicted in Figure IV-12 and Figure IV-13 [69].

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PWM Control for Modular Multilevel Converter

VDC 2

vd

ind

* i nq

VDC 2

i nq

vq

1 sL

i*pd

1 sL

i *pq

VDC 2

vd

i pd

VDC 2

i pq

Figure IV-12: Current loops for the negative part after the de-coupling

vq

1 sL

1 sL

Figure IV-13: Current loops for the positive part after the de-coupling

In the dq0 reference frame, the control of the fundamental component means controlling a constant variable in the time domain. Moreover, a second harmonic component due to the circulating currents, treated in the second chapter, has to be suppressed (Figure II-9). In dq0 this component becomes the fundamental one. The PI regulator (131) is synthetized according to the open loop transfer function shown in (132). The gain ki is evaluated in order to achieve a crossing frequency ten times the fundamental component while the time constant Ti is defined to achieve a phase margin of 60° in order to guarantee the stability.

1 + sTi sTi V 1 1 + sTi Hi( s) = k i ⋅ C . 2 sL sTi

(131)

Ci ( s ) = k i ⋅

V 1 ⎧ Hi ( s ) ω ≈ ki ⋅ C . ⎪⎪ C 2 ωCi L ⎨ ⎪∠Hi ( jωCi ) = a tan ⎛⎜ π ⎞⎟ ⇒ 3 ≈ ωCiTi ⎪⎩ ⎝3⎠

(132)

with

ωCi ≤ 2π (10 ⋅ f 0 ) ωCi iTi >> 1

(133)

The layout of the 0 component control is defined in Figure IV-14 by implementing the third equation of (129) or (130).

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* IDC =3I(*n/ p)0

v(n/ p)0 VDC 2

6 s (3 LL + 2 L )

VDC 2

3I0(n / p)

Figure IV-14: Current controller plant for the 0 component of the structure

The layout of the control loop is depicted in Figure IV-15.

* IDC =3I(*n/ p)0

Ci 0 ( s )

VDC 2

3I0(n / p) 6 s (3 LL + 2 L )

Figure IV-15: Control loop for the 0 component

The regulator (134) makes the system able to follow the power required, for this reason; the dynamic proprieties of the open loop transfer function (135) are slower than the current loop. Therefore, the cutting frequency is around 10 Hz while the time constant is chosen to guarantee the stability (136).

Ci (s) = k i 0 ⋅

1 + sTi 0 sTi 0

Hi 0 ( s ) = k i 0 ⋅ V DC .

(134)

1 + sTi 0 6 s (3 LL + 2 L ) sTi 0

6 ⎧ ⎪⎪ Hi( s ) ωC ≈ ki 0 ⋅ VDC . ω (3L + 2 L) C L ⎨ π ⎪∠Hi( jωCi 0 ) = a tan⎛⎜ ⎞⎟ ⇒ 3 ≈ ωCiTi 0 ⎪⎩ ⎝3⎠

(135)

with

ωCi 0 ≤ 2π ⋅ 15 ωCi 0Ti 0 >> 1

(136)

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IV.2.2.2 Simulations The current control loops are validated via simulations by considering the averaged system with the main parameters listed in Table II-2. The simulations are performed according to the power excursion in Figure IV-16, from inverter to rectifier operating mode always at unit power factor. The dq currents measured in the system seem to match quite well with the references. The stability and the crossing frequency imposed by the regulators guarantee the stability and good shape of the waveforms.

ind* [A]

ind [A]

ipd* [A]

ipd [A]

600 400 200 0 -200 -400 -600 P [W] 100M 50M 0M -50M -100M 1.8

2

2.2 Time (s)

2.4

2.6

Figure IV-16: d-currents with the references and active power

In Figure IV-18 and Figure IV-18 the good synthesis of the regulators is validated even for the q component which is imposed to zero and for the 0 component which is the third part of the DC current.

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inq [A] 20 0 -20 -40 ipq [A] 40 20 0 -20 1.5

2

2.5

3

Time (s) Figure IV-17: Components for q-currents

I0n

I0p

200 0 -200 1.8

2

2.2 Time (s)

2.4

2.6

Figure IV-18: q0-current references and measurements

Finally the u, v, w current components in the branches are reported for the two parts of the system. As verified before, the 0 component regulator was also very well synthesized.

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inu [A]

inv [A]

inw [A]

ipu [A]

ipv [A]

ipw [A]

Id/3 IDC [A]

500 0 -500 [A] IId/3 DC [A]

500 0 -500 1.8

2

2.2

2.4

2.6

Time (s)

Figure IV-19: u, v, w current components in the branches and continuous current

IV.2.3 Branch energy balancing This part of the control regulates the active power necessary to keep the capacitor voltages on a required level. The averaged system in Figure IV-2 is considered. For each part of the system (positive and negative) the DC mean capacitor voltage of the three branches VCn/p is given by (137).

VC n =

(

1 (VCnu + VCnv + VCnw ) ; VC p = 1 VCpu + VCpv + VCpw 3 3

)

(137)

In the dq0 reference frame, considering the PLL latched on the phase voltage, the active and reactive powers, managed by each part of the structure, are achieved in (138). The achieved balance affirms that the active power depends only on the direct component of the AC current and of the AC voltage. The AC voltage is imposed by the grid. The control of the active power is achieved by the regulation of the direct component of the current.

(

)

⎧ PAC ( n / p ) = 3 v d i ( n / p ) d + v q i ( n / p ) q ⎧ PAC ( n / p ) = 3v d i ( n / p ) d ; =⎨ ⎨ ⎩ Q (n / p) = 3 v d i(n / p)q − v q i(n / p)d ⎩ Q ( n / p ) = 3v d i ( n / p ) q

(

)

(138)

Assuming that the negative and positive parts of the structure are balanced between them, the active power is shared in the structure according to the (139). The equivalent capacitance 102

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MODULAR MULTILEVEL CONVERTERS FOR HVDC POWER STATIONS

of each branch is considered as discussed in the second chapter (C/N) by taking into account the AC in (138) and the balance (139) becomes the (140).

P C d VC ( n / p ) (t ) ⋅ VC ( n / p ) (t ) ; PACn = PACp = AC 2 N dt d 2 = C VC ( n / p ) ( t ) dt

PDC = PACn + PACp + 2

(139)

PDC − 6v d i( n / p ) d

(140)

A constant value of the capacitor voltage requires a current with a null DC component as discussed in the second chapter. Hence, we have a direct relationship between the DC and AC currents of the system recalled by (24) in the dq0 reference frame. AC and DC current components in the system are dependent.

i0 =

Mi d cos(ϕ ) 4

(141)

IV.2.3.1 Design of the controller The synthesis was developed by considering the layout in Figure IV-20 valid for the negative and the positive structure according to the (140). The gain of the loop was fixed by considering vd equal to the peak value of the voltage (16).

(V )

2 * C(n/ p)

i(*n / p ) d

6 2V

(V )

2

N sC

C(n/ p)

Figure IV-20: Branch energy control loop

By considering the voltage regulator (131), the open loop transfer function of the system is reported in (143). The control system guarantees the right energy balancing, for this reason the PI regulator is chosen to achieve a low crossing frequency and by ensuring the stability (144).

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Cv (s) = k v ⋅

1 + sTv sTv

Hv( s) = kv ⋅ 6 2V .

(142)

N 1 + sTv sC sTv

(143)

N ⎧ Hi ( s ) ω ≈ k v ⋅ 6 2V . ⎪⎪ C ωCv C ⎨ π ⎪∠Hv( jωC ) = a tan ⎛⎜ ⎞⎟ ⇒ 3 ≈ ωCvTv ⎪⎩ ⎝3⎠

with

ωC ≈ 2π 10 ωCvTv >> 1

(144)

IV.2.3.2 Simulations Simulations were carried out in order to verify the good synthesis of the energy balancing regulators. The main parameters of the system are reported in Table II-2. Simulations are performed by considering the power excursion in Figure IV-21, keeping a null reactive power. The direct components of the current references are generated by the voltage control as depicted by the macro-layout for of the control in Figure IV-3. By requiring a DC current of 650 A (necessary to achieve 100 MW), the voltage controllers generate the right reference by ensuring the right level of the d-component for each branch current (24) for the two parts of the structure (Figure IV-21).

-Pa 100M 50M 0M -50M -100M -150M ind [A]

ind* [A]

ipd [A]

ipd* [A]

400 200 0 -200 -400 1.5

2

2.5

3 Time (s)

3.5

4

4.5

Figure IV-21: Output of the energy balancing controller and direct component of the current for the negative and positive part; power flow

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The voltage value on the averaged cell capacitors is kept constant as shown in Figure IV-22.

Vcnu [V]

Vcnv [V]

Vcnw [V]

Vcpu [V]

Vcpv [V]

Vcpw [V]

170K 165K 160K 155K

170K 165K 160K 155K 1.5

2

2.5

3 Time (s)

3.5

4

4.5

Figure IV-22: Averaged capacitor voltages

IV.2.4 Cell voltage balancing To balance each cell on the desired voltage value a proportional corrector is chosen as was described in [63]. For each branch the controllers are achieved according to Figure IV-23. The control adds an offset dα to the duty cycle imposed by the previous controller and it is placed according to the control plant in Figure IV-3. Because the balance locally interferes on the single cell it is necessary to take in account the direction of the current. In this way, according to the references imposed in Figure IV-2, if the current is positive and the voltage of the cell capacitor is low, the regulator increases the time in which the capacitor is connected to the branch until when is reached the required value and vice-versa.

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Figure IV-23: Capacitor voltage balancing diagram in a branch

The constant of the regulator kC (145) is evaluated to achieve at most 5% of the maximum value of the duty cycle where ∆VCi is the amplitude of the capacitor voltage determined by the value of the capacitance of the cell (6 mF to achieve 10% of voltage ripple).

k C ⋅ ΔVCi

α max

≈ 5%

(145)

IV.2.4.1 Simulations To perform the simulations, the instantaneous model in Figure IV-4 was considered. More details are reported in Table II-2. A resistance is imposed in parallel (2.5 kΩ) for a cell capacitor in order to unbalance its voltage VC1u to 2375 V. On the other hand the energy balancing loop forces the voltage on another cell of the same branch, in this case VCu2 , to increase up to 2625 V in order to reestablish the balance. The simulation view in Figure IV-24 starts with the cell balance enabling. According the sign of the current, Figure IV-24 shows the intervention of the first regulator dα1u in order to decrease the voltage amplitude by considering a positive DC current. The opposite intervention, for a less voltage amplitude, is carried out for VC2u by dα2u. The same results, starting from the same capacitor voltage value, for a negative DC current are shown in Figure IV-25.

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Voltage [V]

3000

2500

VC1u VC1u

2000 0

0.02

0.04

0.06

0.08

0.1 0.12 Time [s]

0.14

0.16

0.18

0.2

0.08

0.1 0.12 Time [s]

0.14

0.16

0.18

0.2

0.05 dα 1u

0

dα 2u

-0.05 0

0.02

0.04

0.06

Figure IV-24: Capacitor voltages and outputs of the cell balancing regulator dα for a positive DC current

Voltage [V]

3000

2500

VC1u VC2u

2000 0

0.02

0.04

0.06

0.08

0.1 0.12 Time [s]

0.14

0.16

0.18

0.2

0.08

0.1 0.12 Time [s]

0.14

0.16

0.18

0.2

0.05 0

dα 1u dα 2u

-0.05 0

0.02

0.04

0.06

Figure IV-25: Capacitor voltages and outputs of the cell balancing regulator dα for a negative DC current

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IV.3 Conclusions For multilevel structures a very low switching frequency can be obtained for each elementary converter due to the phase shifted carriers of the PWM modulation. For a high number of levels however there is an inferior limit of the switching frequency per switching device. In fact the averaged value of the capacitor current of the elementary converter has to be kept at zero. This is guaranteed for a switching frequency not less than 200 Hz. This means that at current parity, the device losses can’t be further reduced. For staircase based modulations, particularly when the number of levels is very high, the equivalent switching frequency can be further reduced up to 90 Hz [75]. This improves performances of the devices in terms of losses. For both the modulation techniques a centralized control is necessary. This means that all the signals of the system, currents and capacitor voltages, must be connected to a central controller. For a high number of levels a very complex hardware is required to wire each capacitor voltage to the central controller and, vice-versa, to wire the driving signal from the controller to the switching devices. For these reasons the trend could be to provide a central controller which manages just the control of the currents and each cell provides itself with voltage, maybe according the surrounding ones.

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Chapter V. The 10 kW modular multilevel prototype

In order to validate the sizing of the components and the control approach a three phase prototype of 10 kW was made. The structure is composed of 18 elementary cells. Each cell is sized to sustain a 200 V capacitor voltage. IGBTs were chosen as switching devices. The converter is configured to test the single loop structure proposed in the third chapter and then, to validate the control loop in the dq0 reference frame and described in the previous chapter. In a first step, the converter was configured in a single loop structure using for each branch a RL load in series to the elementary cells. This is an intermediate configuration, which serves a double purpose. The classical MMC is well known for its much-reduced capability of limiting the branch current in faulty conditions [76]-[77] so it was not preferred for a first test. The RL series connected load instead limits the current in the branches by guaranteeing the setup of the signal chains and the validation of the synthesis of the regulators in safety conditions. Moreover, this configuration reinforced the study of the single loop topology for which experimental results are presented. In a second step, the classical MMC is tested in open loop conditions and experimental results are reported.

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V.1 The prototype configuration The prototype was developed at the LAPLACE laboratory. It is a 10 kVA three-phase modular multilevel converter composed of 18 switching cells. On this basis each branch has 4 voltage levels (0, VDCcell, 2VDCcell, 3VDCcell). Otherwise for a single loop configurations, two branches are directly in series and 7 voltage levels can be achieved (0, VDCcell, …, 6VDCcell). A diagram of the converter is shown in Figure V-1. The layout also shows the installed voltage and current sensors. The rating data is summarized in TABLE V-1.

Figure V-1: Layout of the prototype

10 kW system The Power supply Power Rate 10kVA Model TDK-Lambda ® Genesys VDC 600V Power 5 kW VDCcell 200V DC max. out voltage 600 V L 5mH DC max. out. current 8.5 A C 2mF Cell fsw 2kHz IGBT IRGP35B60PDPBF 60A 600V – TO 247 Case TABLE V-1: 10 kW system parametres

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The power supply can reach up to 5 kW that is the half of the power rating of the system. This value is sufficient to achieve the preliminary tests which concern the set-up of the sensor chains and the validation of the control loops.

V.1.1

Reactive elements design

The design was achieved according to the considerations carried out in Chapter II. The value of the inductor L is chosen in order to limit the current ripple in the branch at switching frequency. Particularly, for this prototype a maximum current ripple of 10% was allowed. vu is the phase voltage imposed by the converter on each phase. Equation (146) considers a maximum modulation index M of 0.9.

V = 0.9

VDC 2 2

= 190V

(146)

The rms current on the AC side at fundamental frequency can be expressed as (147) where P is the power of the converter.

I=

P = 17.5 A 3V

(147)

As previously evaluated, the inductor must respect the balance in (148), for practical reasons an inductance L=5 mH was chosen with a rating of 20 A

L>

VDC 600 = = 3.4mH 2 4 N f c ΔI max 8 ⋅ 3 ⋅ 2000 ⋅ 2.4 2

(148)

A capacitor of 2 mF was chosen as it limits the voltage ripple at fundamental frequency under 10%. Each cell is designed to require an optical signal for the driving of the semiconductor devices. The design of the frame, the PCB of the single cell, the arrangement of the sensors and the power supply for the signal management are described in Appendix A. The final frame for the power side of the converter is shown in Figure V-2.

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Figure V-2: Power Hardware frame

V.1.2

Hardware In the Loop configuration

In this section a description is given on the most important parts of the system, which allows the control implementation and tests. As shown in Figure V-3, the configuration, besides the multilevel prototype, is composed of a HIL box, which allows implementing the control system through a PC. The HIL box accepts analogical signals and sends digital signals to the prototype through the interfacing hardware designed for the purpose. The interfacing hardware allows managing the signals in two directions. In one direction it processes and adapts the analog signals coming from the prototypes’ sensors for the HIL box input. In the other direction the interfacing hardware converts the digital drivers coming from the HIL box in optical signals to control the cells. A more detailed description of these components is given in Appendix A.

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Figure V-3: HIL configuration Lay out

The final assembly of the system with a passive RL load is shown in Figure V-4.

Figure V-4: Final assembly for the system

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In the next section the modular structure is configured in single loop modality. A passive load is connected to the system. After a brief explication of the load choice, the control approach is shown and the synthesis of the regulators is carried out. Experimental results are used to validate the study.

V.2

Single Loop Configuration

The structure is organized as shown in Figure V-5. Due to the unipolar proprieties of the single cell this system imposes also a DC component on the load. For this reason this arrangement can be considered a preliminary configuration before connecting the zig-zag transformer introduced in Section III-2. The configuration was useful to set-up the sensors and to confirm the good correspondence between the simulations and the experimental results with respect to the regulator synthesis. For the tests, a 4 kW three-phase load was used.

IDC

V1

Elementary Cell 1

V2

iL1 V7

Elementary Cell 7

Elementary Cell 2

V8

V3

Elementary Cell 3

iL3 V13

Elementary Cell 13

Elementary Cell 8

V14

Elementary Cell 14

V9

Elementary Cell 9

V15

Elementary Cell 15

V4

Elementary Cell 4

V10

Elementary Cell 10

V16

Elementary Cell 16

V5

Elementary Cell 5

V11

Elementary Cell 11

V17

Elementary Cell 17

V6

Elementary Cell 6

V12

Elementary Cell 12

V18

Elementary Cell 18

v bu

v bv

iL5

v bw VDC

LL

LL

LL

RL

RL

RL

Figure V-5: Prototype in Single Loop Configuration

In order to evaluate the value of the resistance RL to achieve the fixed power, the branch currents (149) and voltages (150) are defined by neglecting the voltage drop on the inductor.

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I DC ⎧ ⎧ ⎪ iL1 = 3 + I 2 sin(ω0t − ϕ ) ⎪ vbu = VDC − V 2 sin(ω0t ) ⎪⎪ ⎪⎪ 2 I DC 2 vbv = VDC − V 2 sin(ω0t − π ) + I 2 sin(ω0t − ϕ − π ) ⎨ ⎨iL3 = (149) 3 3 3 ⎪ ⎪ I 2 ⎪v = V − V 2 sin(ω t + 2 π ) ⎪i = DC + I 2 sin(ω t − ϕ + π ) DC 0 0 L5 ⎪⎩ bw ⎪⎩ 3 3 3

(150)

The power of each branch is balanced according to (151) (in each cell AC and DC power must be balanced according to III.1), so the balance for the total active power is given by (152). By considering a SPWM modulation and the relationships achieved in Chapter II for the single cell, M is considered the amplitude of the modulation index.

cell cell = −PAC = −VI;V = PDC

VDC ⋅ I DC = 3Pcell

VDC

M (151) 2 2 I2 I2 + 3 ⋅ RL DC + 3 ⋅ RL I 2 + 3 ⋅ VI ⇒ VDC ⋅ I DC = +3 ⋅ RL DC + 3 ⋅ RL I 2 (152) 9 9

By taking in account (151), in (153) the value of I is reported.

I= 2

I DC 3M

(153)

By substituting (153) in (152), (154) is achieved.

2 ⎞ 2 ⎞ ⎛1 ⎛1 VDC = RL I DC ⎜ + Req = RL ⎜ + 2 ⎟; 2 ⎟ ⎝ 3 3M ⎠ ⎝ 3 3M ⎠

(154)

So the control matches the impedance through the variation of M in order to achieve the required power. In this case RL is defined by the resistor bench available in the laboratory which allows up to 4 kW operating power. According to the relationships achieved before, TABLE V-2 reports the main operating parameters. The inductor LL was chosen to test the good current ripple around the 5%.

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Single loop system parameters Operating power VDC RL Req IDC M LL Number of cells N per branch

4 kW 600 V 40 Ω 90 Ω 6.7 A 0.6 5 mH 6

TABLE V-2: system parameters for the single loop configuration

In the next section the control approach is described and the synthesis of the controller is carried out.

V.2.1

The control

A simple u, v, w frame is considered and a superposition approach is used to simplify the study. By considering the averaged model, the DC current loops are shown in Figure V-6 while the AC loops are reported in Figure V-7.

IDC=0

IDC DC vbu

vbvDC

DC vbw

I DC 3

I DC 3

I DC 3

LL

LL

LL

RL

RL

RL

vbuAC AC

Figure V-6: Layout of the DC part of the system

AC vbw AC

AC

I L1

VDC

vbvAC I L5

I L3 LL

LL

LL

RL

RL

RL

Figure V-7: Layout of the AC part of the system

By considering the single cell topology the voltage imposed by each branch is reported in (155) according to the averaged system in Figure V-8 for a generic phase (u, v or w). On the DC approach, the branch imposes the voltage to balance the DC side according to (156). The AC voltage value is determined by the modulation index M given in (157). The voltage on the equivalent capacitor is provided by (158). 116

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vb

Vc = 2VDC

vb =

vbDC AC b

v

NVC ⋅ (1 + M sin(ω0 t ) ) 2 = VDC ⇒ NVC = 2VDC

= M ⋅ NVC sin(ω0t )

VC =

(155) (156) (157)

N

1 ∑VCj N j =1

(158)

Figure V-8: Averaged model of the branch cells

According to the control strategy for the multilevel structures depicted in Figure IV-3 (previous chapter) PI regulators are synthetized. The current control loop is highlighted in Figure V-9, where in this case the gain of the system is 2VDC. The PI regulator is synthetized in order to achieve a crossing frequency of 1 kHz while the time constant is defined to achieve a phase margin of 60° in order to guarantee the stability.

1 sL

i L* iL

Figure V-9: Current control loop

The branch energy balancing generates the active reference current necessary to keep a total voltage on the capacitors of 2VDC where C/N is the equivalent capacitance of each branch. The PI regulator is chosen to achieve a low crossing frequency by ensuring the stability.

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(2V )

I(*u,v,w)

* 2 DC

N sC

(V )

2

C

By considering the instantaneous model, the same strategy already described in the previous chapter was adopted to keep a constant voltage of 2VDC/N on each cell capacitor. This because the cell voltage balancing is a parallel loop which depends neither from the current nor from the branch energy balancing loops but it directly interferes on the modulation index. One more time each cell capacitor has 200V voltage.

V.2.2

Simulations

For the single loop system previously described, TABLE V-2 reports the main parameters and its layout is highlighted in Figure V-5. The levels imposed by the cells (Figure V-10) in the system are limited to 5 levels because the modulation index M is equal to 0.6. The maximum number of levels 7 is reached for a value of M almost equal to 1.

Vbu [V] 800 600 400 200 0 Vbv [V] 800 600 400 200 0 Vbw [V] 800 400 0 0.86

0.88

0.9

0.92 Time (s)

Figure V-10: Voltage imposed by each branch

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The currents in the branches and the DC current are shown in Figure V-11. The current ripple, kept below the desired value, confirms the right evaluation of the branch inductor.

iL1 [A]

iL3 [A]

iL5 [A]

idc [A]

10

5

0

-5 0.86

0.88

0.9

0.92

0.94

Time (s)

Figure V-11: Branch currents and DC current

The voltage on the cell capacitors kept at the desired value validates the single cell balancing as shown in Figure V-12.

V1 [V]

V2 [V]

V3 [V]

V4 [V]

V7 [V]

V8 [V]

V9 [V]

V10 [V]

V5 [V]

V6 [V]

201 200.5 200 199.5 199 V11 [V]

V12 [V]

201 200.5 200 199.5 199 V13 [V]

V14 [V]

V15 [V]

V16 [V]

V17 [V]

V18 [V]

201 200 199 1.02

1.04

1.06 Time (s)

1.08

1.1

Figure V-12: Voltages on the cell capacitors

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The perrformed sim mulations validate v thee study forr this confiiguration off the system. Experimen ntal results arre reported in i the next ssection.

V V.2.3

Exp perimenta al results

The testts confirm the t good op peration of tthe sensor chains c and the t good syynthesis of the t regulators. The acquisiitions are dissplayed by cconsidering a time scale of 5ms/divv.

Figure V-13: Bra anch voltages aand currents on o DC side and d phase u.

Fig gure V-14: Bran nch voltages an nd currents

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208

V1

Voltage [V]

206

V2

204

V3

202

V4 V5

200

V6

198 196 194 0.005

0.01

0.015

0.02 0.025 time [s]

0.03

0.035

0.04

Figure V-15: Cell capacitor voltages

The experimental results seem to match quite well with the simulations. The voltages imposed by the branches confirm one more time the correct phase shift between the carriers. Moreover all the levels are not reached because the amplitude of the modulation index is around 60%. The achieving of the power required validates the good choice of gains for both the regulators for the energy balancing and current loops. The stability of the system is guaranteed by the phase margin which validates the values of the time constants. Finally the parallel loop for the cell voltage balancing interferes without influencing the stability.

V.3 MMC configuration The MMC configuration of the prototype is considered. For the simulations in closed loop, the multilevel structure is connected to a three-phase voltage source (Figure V-16). For the experimental results, an open loop control is considered with a RL load (Figure V-20).

V.3.1

Simulations in Closed Loop operation

Because of the network connection the simulations were performed for the full 10kW power system of which parameters are reported in V.1. An excursion is carried out at unity power factor by leading the system during operation from inverter to rectifier mode.

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V1

Elementary Cell 1

V2

Elementary Cell 2

V3

IL1 V7

Elementary Cell 7

V8

Elementary Cell 8

Elementary Cell 3

V9

V4

Elementary Cell 4

V5

Elementary Cell 5

V6

Elementary Cell 6

vnu

v pu IL2

vu

IL3 V13

Elementary Cell 13

V14

Elementary Cell 14

Elementary Cell 9

V15

Elementary Cell 15

V10

Elementary Cell 10

V16

Elementary Cell 16

V11

Elementary Cell 11

V17

Elementary Cell 17

V12

Elementary Cell 12

V18

Elementary Cell 18

vnv

v pv IL4

vv

IL5

vnw

VDC

v pw IL6

vw

Figure V-16: MMC system configured for the simulations

The u, v, w currents are shown in Figure V-7. During the excursion the stability of the system is maintained. Also the stability of the DC current confirms the good synthesis of the current regulators. Moreover the right active power is required by the regulator synthetized for branch energy balancing loop.

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iL1 [A]

iL3 [A]

iL5 [A]

Idc

iL2 [A]

iL4 [A]

iL6 [A]

Idc [A]

20 10 0 -10 -20

20 10 0 -10 -20 0.8

1

1.2 Time (s)

1.4

1.6

Figure V-17: Branch currents and DC current

The branch voltages in Figure V-18 show how all the four switching levels are reached. This validates the good phase delay between the SPWM modulation carriers.

Vnu [V]

Vnv [V]

Vnw [V]

Vpu [V]

Vpv [V]

Vpw [V]

600 400 200 0

600 400 200 0 0.5

0.52

0.54

0.56

0.58

0.6

Time (s)

Figure V-18: Voltages imposed by the branches

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voltage [V]

Finally the averaged voltages on the cell capacitors are kept on 200 V. This validates the balancing of the single cell voltage.

V1

210

V2 V3

200

V4 V5

190

V6

0.8

0.9

1

1.1

1.2 1.3 Time [s]

1.4

1.5

1.6

1.7

voltage [V]

215 210

V7

205

V8

200

V9 V10

195

V11

190

V12

185

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

voltage [V]

Time [s] V13

210

V14 V15

200

V16 V17

190

V18

0.8

0.9

1

1.1

1.2 1.3 Time [s]

1.4

1.5

1.6

1.7

Figure V-19: Voltages on the cell capacitors

V.3.2

Open Loop-Tests

The tests were carried out for the maximum capability of the power supply (5 kW). The MMC configuration is connected to the RL load according to the layout shown in Figure V-20. The resistive load is composed of two 4 kW test benches in parallel to achieve the power

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necessary for the tests. The final resistance star configured has a 40 Ω value in order to achieve 4.8 kW. IDC

V1

Elementary Cell 1

V2

Elementary Cell 2

V3

IL1 V7

Elementary Cell 7

V8

Elementary Cell 8

Elementary Cell 3

V9

V4

Elementary Cell 4

V5

Elementary Cell 5

V13

Elementary Cell 13

V14

Elementary Cell 14

Elementary Cell 9

V15

Elementary Cell 15

V10

Elementary Cell 10

V16

Elementary Cell 16

V11

Elementary Cell 11

V17

Elementary Cell 17

V6

Elementary Cell 6

V12

Elementary Cell 12

V18

Elementary Cell 18

vnu

v pu

IL3

vnv

v pv

IL5

vnw VDC

v pw

IL4

IL2

LL

vu

IL6

LL

vv RL

LL

vw RL

RL

Figure V-20: MMC system configured for the experimental tests

The currents in the negative branches are depicted in Figure V-21. In open loop each branch current presents a DC and a second harmonic component of the fundamental. .

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Figure F V-21:N egative branch h current

As show wn in Figuree V-22, the currents in the negativ ve and positiive branchees are in pha ase opposition in terms of o fundamen ntal compo onent. Also the sum between them m is reportted according tto the refereences shown n in Figure V V-20. The su um has a DC C and a seccond harmon nic componentt which has to be suppreessed by the closed loop p control.

Figure V-22 2: Negative, poositive branch current c and the e sum

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The value of the DC current c arou und 8A conffirms an ope erating poweer of the sysstem around d 4.8 kW (Figu ure V-23). The T output AC currentts (Figure V-23) V have a sinusoidall waveform.. his means that t both th he componen nts DC and d second harmonic are kept in thee branch forr Th eaach phase. The curren nt ripple is further redu uced because of the pphase shift modulation n technique. In fact the gro oup of carrieers for the ceells of the positive part is phase shiifted respectt o the group of o the negatiive part. to

Figure V-223: Output AC C currents and DC current

v valiidate the corrrect phase shift amongg The 4 voltage levels acchieved for tthe branch voltages th he carriers off each cell (F Figure V-24)).

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Figu ure V-24: Negattive branch volltages and currrent in the negative branch

Figure V V-25 shows the positivee and negatiive branch voltages v for the u-phasee. As expectted the voltagees have the same DC co omponent. The AC components complement c t each other at the fundam mental frequeency.

F Figure V-25: Neegative and po sitive branch voltages, v branch current

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The zoom m of Figure V-25 V shown in Figure V-26 V validate es the right pphase shift between b thee ceells of the negative n bra anch and th he cells of th he positive branch. Fuurthermore, the currentt rip pple amplitu ude confirm ms the right ssizing of thee branch ind ductors whicch guarantees a currentt rip pple under 10% 1 (the ind ductor is rateed for a currrent of 20 A)).

Figure V-26 : Zoom on volltage and current waveforms

Finally so ome capacitor voltages are shown n in Figure V-27. The voltages arre balanced d beetween them m, they have the same D DC componeent value of 200 V.

Figure V-227: Capacitor voltages v and bra anch current

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The 10 kW modular multilevel prototype

V.4 Conclusions Experimental validations for the single loop structure will allow an immediate transition to the configuration with the zig-zag transformer. The closed loop tests ensured the good correspondence between the sensors and the input analog signals to the controller (HIL Box). Moreover, each output modulation signal coming from the controller drives the right device. The wiring of the switching signals by optical fiber considerably reduced the EMI problems. The stability of the tested closed loop system validates the reliability of the simulation results by confirming the right synthesis of the regulators. This aspect will facilitate the closed loop tests for the MMC structure. Of course this case is always more dangerous just because the branch inductor limits the current in emergency conditions (divergence of the control, faults etc). These tests will be performed in the coming month.

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Conclusions & Future Prospects Nowadays HVDC connections are an appropriate answer to the more and more increasing world energetic demand. Multilevel topologies are going to make VSC converters the most employed in HVDC systems. The development of high voltage controlled turn-off devices made these structures very attractive. On the other hand because of advantages coming from the easily series connections of thyristors, CSC structures can better manage high voltages. In the near future, the gap between VSC and CSC structures will be much reduced thanks to the performances offer by IGCT devices in terms of on-state current rating and blocking voltage. The press packaging leads a series of advantages respect to the classical modules especially in fault condition where there is a risk of explosion. The single wafer feature makes the IGCT more suitable for the press pack packaging respect to the IGBT. For these reasons the IGCT seems to be the most attractive device in VSC-HVDC applications. This thesis focused on the VSC based Modular Multilevel Structure. For preliminary studies the “macro-model” allowed direct evaluations and very fast simulations especially as this model is not dependent on the elementary converter topology. The rating of the system was carried out through two control approaches. The first considers just a control on the AC output current which leads to a huge second harmonic current in the branch. We showed that Coupled inductors could be a good solution to limit this current but in the field of high power applications, the particularity of this hardware increases absolutely the cost. Thus, the second approach consists in a control of each current in the branch, despite it requires a more efficient control system based on a dq reference frame. Under this condition the second harmonic component of the current is cancelled which cut down the rating of the passive components. The employment of different topologies as elementary converter made the MMC more flexible in terms of voltage and current reversibility. In terms of losses at parity of power and DC voltage, the simple cell is more convenient. Unlike topologies which provide bipolar voltage (Asymmetrical HB and full H-bridge) make the structure able to limit the short-circuit current in case of fault on the DC link. The Phase Shifted PWM led to a reduction of the switching frequency and then the semiconductor losses. Of course this modulation technique presents an inferior limit on the switching frequency. When the number of levels is very huge the staircase modulation could be very attractive for multilevel structures. A study of the staircase modulation for the MMC structure is going to be soon developed. In fact an investigation on the influence of the modulation versus the rating of the reactive elements and versus power losses of the devices compared to the PS PWM left to be done. Few aspects could make the Asymmetrical HB attractive in terms of HVDC applications. If this topology is chosen, the cell capacitor can be reduced at parity of voltage ripple amplitude. 131

Conclusions & Future Prospects Since the system achieves the inversion of the power flow by changing the polarity of the DC voltage, this topology can be employed to replace CSC based HVDC power stations with the advantage of a unit power factor operation. The new single loop structure proposed in chapter III allows an easier control system. The topology does not require the double branch inductor because it uses the leakage inductor of the zig-zag coupling transformer. Although this coupling requires more copper than a classical winding, the insulation of the transformer has to be rated only for the AC voltage. This is not the case of a classical MMC arrangement where the transformer has to sustain a DC insulation half of the DC voltage (DC zero sequence component). Beyond these considerations, the use of this new structure could become very attractive to upgrade old rectifiers by guaranteeing advantages coming from VSC structures. A 10 kW prototype was developed in the LAPLACE laboratory. In order to interface the power circuit with the Hardware In the Loop system a boards console placed on the frame called “Interfacing Hardware” was achieved. The interfacing hardware adapts the voltage levels of the signals coming from the sensors of the prototype to the input voltage level at of the HIL box. Moreover it provides also the noise filtering for the analogical signals. Even for the output digital signals coming from the HIL box an electric-optical conversion is provided by the Interfacing Hardware to control the cells. Before starting the power tests, a preliminary procedure was carried out. All the sensors were calibrated and the good wiring of the signal chain was verified. Finally the optimization of the grounding configuration of all the system was improved step by step in order to avoid EMI problems. Experimental validations in SPWM were achieved for the single loop topology and the classical structure. The good operation of the control loops validated the system modeling approach and the regulator synthesis. In the near future, this prototype will allow testing the single loop structure with the zig-zag transformer, the closed loop operation in a dq frame and the staircase modulation.

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APPENDIX A - The Prototype: Design & Development A.1 The Elementary cell In this section the elementary switching cell of the MMC converter prototype is described. A simple scheme is reported in Figure A - 1.

Figure A - 1: Scheme of the elementary switching cell

Each of the 18 switching cell is composed by the following main components: ƒ ƒ ƒ ƒ ƒ ƒ

2IGBT IRGP35B60PDPBF 60A 600V – TO 247 Case 1 IGBTs Driver CONCEPT 2SC0108T 1 Voltage sensors 1 Capacitor 2mF (2x1mF) (450V) 1 optic fiber receiver for switching signal Power supply TRACO TMS 15215

The elementary switching cell is equipped by a single optic fiber receiver. On the cell, a logic circuit generates the 2 complementary switching signals for the BOT and the TOP IGBT. Moreover, a circuit for managing the dead time is present. Particularly this is designed to give a dead time of 2μs.

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Each ceell is equipp ped by a LE EM voltage sensor that measures th he capacitorr voltage. The T LEM senso or gives the measure in current. It iis designed to t give 25m mA for a meaasured volta age of 200V.

All the electronics on the PCB is supplieed by a TR RACO conn nected to thhe 230V 50H Hz network.

Figure A - 2 show ws the dimeensions of tthe cell PCB B with the componentts dispositio on. Moreover F Figure A - 3 and Figure A - 4 report rt the TOP and a BOTTOM layers off the PCB. The T final realizaation for thee cell is reported in Figu ure A - 5.

Figure A - 2: Disposittion of compon nents on the ce ell

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F Figure A - 3: PCB P Top layer

Figure A - 4: P PCB Bottom la ayer

The cells are a posed in n group of 3 on a single heat sink. Finally F the hheat sink aree assembled d in n group of 3 forming a matrix m of cellls 3x3 as sho own in the picture p of Fig igure A - 2.

Figure A - 5: Photo off a cell

Figure e A - 6: Cells onn the heatsinkss

V.4.1

Meassurement Cards

Each boarrd is equipped with a vvoltage senso or and two current sennsors, to ach hieve all thee reequired meaasurements four board ds were installed. Adaptation annd filtering stages aree acchieved by the acquisittion cards w which are detailed d bellow. The reeference circcuit for thee m measurementts achieved on o the proto otype is repo orted in Figu ure A - 7

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Fiigure A - 7: Meeasurement carrd lay-out and its definitive re ealization

A.2 Th he Fram me From Fiigure A - 8 to t Figure A - 10 few vieews of layou ut of the fram me prototypee are reporteed. The detaileed descriptio on of the power stage w with the elem mentary cellss features w was given in R1. Capacito or voltages and a branch currents arre provided by sensors (LEM) ( and measuremeent cards adaptt output sensor voltagess to the hard dware inputss.

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Figgure A - 8: Top p view of the frrame

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Figurre A - 9: View of the design for f the frame

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Figurre A - 10: CAD D design of the system

The interffacing hardw ware platforrm shown in n Figure A - 11 is com mposed by sorting s card d w which provid des to adapt the analoggical signals coming fro om the acquuisition card ds, sorted in n ur, to the DB37 connecctor. Moreov ver the digital signals ccoming from m the DB37 7 grroups of fou co onnector aree divided in groups of eeight signalss which are converted inn optical sig gnals by thee op ptical emitteer. In the nextt paragraphss each board d of the interrfacing platfform is descrribed.

139

140

18

6

Figure A - 11: Interfacing Hardware platform DB37M 4

12 6 DB37M 3

From OPAL-RT

Aquisition Card 4

Optical Emitter 1

Voie [0...5]

6

Sorting Card

Aquisition Card 3

Optical Emitter 2

Voie [0...5]

DB37M 2

16

16 To OPAL-RT

DB37M 1

Aquisition Card 2

4

Optical Emitter 3

JA

JB

VOUT 1..4

From Measurements

Aquisition Card 1

VOUT 5..8

6

Voie [0...5]

APPENDIX A The prototype: Design & Development

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A A.1.1 Acqu uisition Card C

Each boarrd allows ad dapting the signals com ming from th he measurem ment cards to the rightt levvel [±15V] for the anallog input sid de of the OP5340 O for the t OPAL-R RT frame. Each E card iss abble to processs eight signals by elimin nating the noise n whit tu unable high frequency active a filters.. To o process 29 9 analog measurements four acquisition cards are a employeed. The PCB B circuit and d itss final layou ut are depicteed in Figuree A - 12.

Figu ure A - 12 Acqu uisition card la ayout.

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The prototyp pe: Design & Development

A.1.1 Op ptical emiitter

The diggital signalss coming from fr the O OPAL-RT provides p the e ON/OFF F state of the t semiconductor devicess. The signa als are arran nged in three groups, on ne per phasse. The outp put L-RT puts ou ut [0, +5 V] signals. card OP53554 of OPAL Each op ptical emitteer is designed d to convertt in optical signal s up to eight electrrical inputs. In the configu uration adop pted for thee prototype just six way ys are cable ed (Figure A - 13) whiich correspond ds to the num mber of cellss per phase o of the MMC C prototype.

Figure F A - 13: Optical emitteer layout

For thee interfacingg hardware two tabless are provid ded. One table is proovided for the t analogical signal and another one for the digitall signals. Each E tablee reports the t correspond dences, by co onsidering th he levels of cconnection per signal. The T levels arre:

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OP PAL-RT num mber channeel

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Number of the way on the card Number of the card Name of the voltage/current measured

A.2 HIL Box The device chosen for the prototyping is the OPAL-RT 5600, which permits to achieve the following performances.

-

Model-Based design and virtual Prototyping Control Prototyping and testing Embedded Control Data Logging

The OP5600 is a complete simulation system capable of operating with either Spartan 3 or Virtex 6 FPGA platforms. It is designed to be used either as a desktop (or shelf top) or as a more traditional rack mount. It contains a powerful Target Computer and a flexible highspeed Front End Processor and a signal conditioning stage. The new design makes it easier to use with standard connectors (DB37, RJ45 and mini-BNC) which avoid input/output adaptors and allow quick connections for monitoring. The front of the chassis provides the monitoring interfaces and monitoring connectors, while the back of the chassis provides access to the FPGA monitoring connections, all I/O connectors, power cable and main power switch. Inside, the main housing is divided into two sections, each with a specific purpose and connected only by a DC power cable and a PCIe cable: In its standard configuration, the lower part of the chassis contains a powerful target computer that can be connected to a network of simulators or can have a stand-alone capability. The target computer includes the following features:

− − − − −

ATX motherboard with up to 12 cores 6 DRAM connectors 250 Mb hard disk 600 W power supply PCIe boards (up to 8 slots, depending on the configuration).

The main features of the system are reported in [78].

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The prototype: Design & Development

A.3 PIN tables The connections about the interfacing hardware are sorted according table A-1 for the analogic signals.

IL6  VCA        IL3  IL4  VBC  IL5  IL1  IL2  VAB     V17  V18  IDC  VDC 

Gr. 1 Sec.B 

Vout 5  Vout 6  Vout 7  Vout 8  Vout 1  Vout 2  Vout 3  Vout 4  Vout 5  Vout 6  Vout 7  Vout 8  Vout 1  Vout 2  Vout 3  Vout 4 

OPAL‐RT Channel 

3 5 7 9 3 5 7 9 3 5 7 9 3 5 7 9

Signal Name 

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JB  JB  JB  JB  JA  JA  JA  JA  JB  JB  JB  JB  JA  JA  JA  JA 

Signal Name 

TABLE A-1

4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3

HE_10 N°Pin 

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Connector Name

                                               

Aq. Card  Number 

Gr. 1 Sec. A 

1  2  JB  3  Vout 5  V10  0 2  2  JB  5  Vout 6  V11  1 3  2  JB  7  Vout 7  V12  2 4  2  JB  9  Vout 8  V16  3 5  2  JA  3  Vout 1  V15  4 6  2  JA  5  Vout 2  V4  5 7  2  JA  7  Vout 3  V5  6 8  2  JA  9  Vout 4  V6  7 9  1  JB  3  Vout 5  V8  8 10  1  JB  5  Vout 6  V9  9 11  1  JB  7  Vout 7  V13  10 12  1  JB  9  Vout 8  V14  11 13  1  JA  3  Vout 1  V1  12 14  1  JA  5  Vout 2  V2  13 15  1  JA  7  Vout 3  V3  14 16  1  JA  9  Vout 4  V7  15 DB37M Pins 20..35=AGND on Acq. Card 

PIN DB37M_2 

OPAL‐RT Channel 

Signal Name 

Signal Name 

HE_10 N°Pin 

Connector Name

Number 

PIN DB37M_1 

Aq. Card 

0  1  2  3  4  5  6  7  8  9  10  11  12  13  14  15 

                                               

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The connections about the interfacing hardware are sorted according table A-2 for the digital signals.

                       

Elementary Cell 

7 8 9 10 11 12

                       

Voie 7  Voie 6  Voie 5  Voie 4  Voie 3  Voie 2  Voie 1  Voie 0                         

Gr. 2 Sec. B 

     

9 8 7 6 5 4 3 2

                                               

      13 14 15 16 17 18                        

OPAL‐RT  Channel 

1 2 3 4 5 6

3 3 3 3 3 3 3 3

Signal Name 

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

HE_10 N°Pin 

     

Emetteur optique  Number 

PIN DB37M_3 

                                               

Elementary Cell 

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Gr. 2 Sec. B 

Voie 7  Voie 6  Voie 5  Voie 4  Voie 3  Voie 2  Voie 1  Voie 0  Voie 7  Voie 6  Voie 5  Voie 4  Voie 3  Voie 2  Voie 1  Voie 0 

Channel 

9  8  7  6  5  4  3  2  9  8  7  6  5  4  3  2 

Signal Name 

1  1  1  1  1  1  1  1  2  2  2  2  2  2  2  2 

HE_10 N°Pin 

Number 

PIN DB37M_4  1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16 

Emetteur optique  OPAL‐RT 

16  17  18  19  20  21  22  23                         

DB37M Pins 20..35,37=GND on E.O. card; DB37M Pin 18= +5V on E.O. card  TABLE A-2

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References

[1] Hammons, T.J. ; Woodford, D. ; Loughtan, J. ; Chamia, M. more authors, “Role of HVDC transmission in future energy development”, Power Engineering Review, IEEE (Volume:20 , Issue: 2 ), Feb. 2000 [2] S. Alvarez, P. Ladoux, E. Carroll, “Characterisation of Low Voltage IGCTs (3,3KV) by using and Opposition Method Test Bench” PCIM'04 - International Exhibition and Conference for Power Electronics Intelligent Motion Power Quality, NUREMBERG (Allemagne), Mai 2004 [3] IEEE T&D committee 2000 – CIGRE 2000 WG-B4 04 2003 [4] http://www.ece.uidaho.edu/hvdcfacts/Projects [5] Xu, L., & Andersen, B. R. (2006). Grid connection of large offshore wind farms using HVDC. Wind Energy, 9(4), 371-382. [6] http://www.itaipu.gov.br/en/energy/integration-brazilian-system [7] G. Asplund, “Ultra high voltage transmission,” ABB Rev., vol. 2, pp. 22– 27, 2007 [8] U. Axelsson, A. Holm, C. Liljegren, K. Eriksson, L. Weimers, Gotland HVDC Light Transmission – World’s First Commercial Small Scale DC Transmission, Proceedings of the CIRED Conference, Nice, France, May 1999. [9] Flourentzou, N. ; Sch. of Electr. & Inf. Eng., Univ. of Sydney, Sydney, NSW ; Agelidis, V.G. ; Demetriades, G.D., “VSC-Based HVDC Power Transmission Systems: An Overview”, Power Electronics, IEEE Transactions on (Volume:24 , Issue: 3 ). [10] Bijlenga, B. (1999). U.S. Patent No. 5,946,178. Washington, DC: U.S. Patent and Trademark Office. [11] R. Marquardt, A. Lesnicar, J. Hildinger, Modulares Stromrichterkonzept für Netzkupplungsanwendung bei hohen Spannungen, ETG-Fachtagung, Bad Nauheim, Germany, 2002. [12] J. Gerdes, Siemens Debuts HVDC PLUS with San Francisco’s Trans Bay Cable, Living Energy, Issue 5, July 2011, www.siemens.com/energy/livingenergy. [13] Francos, P. L., Verdugo, S. S., Alvarez, H. F., Guyomarch, S., & Loncle, J. (2012, July). INELFE—Europe's first integrated onshore HVDC interconnection. In Power and Energy Society General Meeting, 2012 IEEE (pp. 1-8). IEEE. [14] A. Persson and L. Carlsson, “New technologies in HVDC converter design,” in Proc. AC/DC Power Transmiss., London, U.K., 1996, pp. 387–392, (Inst. Electr. Eng. Conf. Publ.). 147

References [15] L. Carlsson, “‘Classical’ HVDC: Still continuing to evolve,” Modern Power Syst., vol. 22, no. 6, pp. 19–21, 2002. [16] SHU, Y. B., LIU, Z. H., GAO, L. Y., & WANG, S. W. (2006). A Preliminary Exploration for Design of±800kV UHVDC Project with Transmission Capacity of 6400MW [J]. Power System Technology, 1, 000. [17] Kitagawa, M. ; Hasegawa, S. ; Inoue, T. ; Nakagawa, A., ” A 4500 V injection enhanced insulated gate bipolar transistor (IEGT) operating in a mode similar to a thyristor”, Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International Date 5-8 Dec. 1993 [18] Baek, J. W., Yoo, D. W., & Kim, H. G. (2001). High-voltage switch using series-connected IGBTs with simple auxiliary circuit. Industry Applications, IEEE Transactions on, 37(6), 1832-1839. [19] J. Varley, “HVDC: Fifty years on,” Modern Power Syst., vol. 24, no. 10, pp. 18–20, 2004. [20] Giovanni Mazzanti, Massimo Marzinotto, “Extruded Cables for High-Voltage Direct-Current Transmission: Advances in Research and Development”, Wiley September 2013. [21] EIC consultancy, presentation for LAPLACE laboratory, Toulouse 4th February 2013, slide 29 [22] S. Bernet, “Recent Developments of High Power Converters for Industry and Traction Applications”, Transactions on Power Electronics, November 2000, Foz do Iguaçu, Brazil [23] Poller, T., Basler, T., Hernes, M., D’Arco, S., & Lutz, J. (2012). Mechanical analysis of press-pack IGBTs. Microelectronics Reliability. [24] ] H, Matsuda, M. Hipshi and N. Kawamura, "Pressure Contact Assembly Technology of High Power Devices,” hoe. of ISPSD’97, pp.17-24, 1997. [25] Lu, W., & Ooi, B. T. (2003). DC overvoltage control during loss of converter in multiterminal voltage-source converter-based HVDC (M-VSC-HVDC). Power Delivery, IEEE Transactions on, 18(3), 915-920. [26] Kopta, A., & Rahimo, M. (2005, May). The field charge extraction (FCE) diode: A novel technology for soft recovery high voltage diodes. In Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD'05. The 17th International Symposium on (pp. 83-86). IEEE. [27] M.T. Rahimo, P.T. Hoban, N.Y.A. Shammas, "Effects of Temperature, Forward Current and Commutating di/dt on the Reverse Recovery Behavior of Fast Power Diodes", EPE'95, Spain, pp 1.577-1.582., Sept. 1995. [28] H. Grüning, et al. “High-Power Hard-Driven GTO Module for 4.5 kV/3 kA Snubberless Operation” PCIM 96, Nürnberg, May 1996 [29] Ogura, T., Nakagawa, A., Takigami, K., Atsuta, M., & Kamei, Y. (1988). High frequency 6000 V double gate GTOs. In Electron Devices Meeting, 1988. IEDM'88. Technical Digest., International (pp. 610-613). IEEE. igbt explosion [30] Perpina, X. Serviere, J.F. ; Jorda, X. ; Hidalgo, S. ; Urresti-Ibanez, J. ; Rebollo, J. ; Mermet-Guyennet, M. “Over-current turn-off failure in high voltage IGBT

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modules under clamped inductive load”, European Conference on Power Electronics and Applications, 2009. EPE '09. 13th [31] H. Akagi, “Trends in Power Electronics and Motor Drives”, Power Electronics and Drive Systems, 2003. PEDS 2003 [32] S. Gunturi, J. Assal, D. Schneider, and S. Eicher, “Innovative metal system for press pack IGBTs,” in Proc. Int. Symp. Power Semiconductor Devices (ISPSD), Cambridge, U.K., Apr. 14–17, 2003, pp. 110–113 [33] S. Eicher, M. Rahimo, E. Tsyplakov, D.l Schneider, A. Kopta, U. Schlapbach, E. Carrol, “4.5kV Press Pack IGBT Designed for Ruggedness and Reliability”, Industry Applications Conference, 2004. 39th IAS Annual Meeting. Conference Record of the 2004 IEEE (Volume:3 ) [34] S. Gunturi, D. Schneider “On the Operation of a Press Pack IGBT Module Under Short Circuit Conditions”, IEEE transactions on advanced packaging, vol. 29, no. 3, august 2006. [35] E. Carroll, S. Klaka, S. Linder, “Integrated Gate-Commutated Thyristors: A New Approach to High Power Electronics”, IGCT Press Conference, May 20, 1997, IEMDC Milwaukee. [36] Erickson, R. W., & Maksimovic, D. (2001). Fundamentals of power electronics. Springer. [37] Shepherd W., Zhang L., “Power converter circuits”, Marcel Dekker, Inc., ISBN: 0-8247-5054-3, 2004 [38] Naik, R., Rastogi, M., & Mohan, N. (1995). Third-harmonic modulated power electronics interface with three-phase utility to provide a regulated DC output and to minimize line-current harmonics. Industry Applications, IEEE Transactions on, 31(3), 598-602. [39] Schettler, F. ; Huang, H. ; Christl, N., “HVDC transmission systems using voltage sourced converters design and applications”, Power Engineering Society Summer Meeting, 2000. IEEE (Volume:2 ) [40] Fioretto, M. ; Raimondo, G. ; Rubino, L. ; Serbia, N. ; Marino, P., “Evaluation of current harmonic distortion in wind farm application based on Synchronous Active Front End converters”, Africon 2011 [41] Hirose, M., Masuda, T., Sato, K., & Hata, R. (2006). High-temperature superconducting (HTS) DC cable. SEI TECHNICAL REVIEW-ENGLISH EDITION-, 61, 29. [42] Rodriguez, J., Lai, J. S., & Peng, F. Z. (2002). Multilevel inverters: a survey of topologies, controls, and applications. Industrial Electronics, IEEE Transactions on, 49(4), 724-738. [43] Zhang, Yushu; Adam, G.P.; Lim, T.C.; Finney, Stephen J.; Williams, B.W.; “Voltage Source Converter in High Voltage Applications: Multilevel versus Two-level Converters” IET ACDC 2010, London, UK [44] F. Tourkhani, P. Viarouge and T. A. Meynard “A Simulation–Optimization System for the Optimal Design of a Multilevel Inverter” IEEE transactions on Power Electronics, vol. 14, no. 6, November 1999 [45] www.energy.siemens.com 149

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HVDC

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