Aalborg Universitet Steady-State Linear Kalman Filter

b, and vcdenote the three-phase input signals of the PLLs, v and v are the grid voltage signals in the stationary ( ) frame, and v dand vqare the grid...

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Aalborg Universitet

Steady-State Linear Kalman Filter-based PLLs for Power Applications A Second Look Golestan, Saeed; Guerrero, Josep M.; Quintero, Juan Carlos Vasquez Published in: I E E E Transactions on Industrial Electronics DOI (link to publication from Publisher): 10.1109/TIE.2018.2823668

Publication date: 2018 Document Version Accepted author manuscript, peer reviewed version Link to publication from Aalborg University

Citation for published version (APA): Golestan, S., Guerrero, J. M., & Quintero, J. C. V. (2018). Steady-State Linear Kalman Filter-based PLLs for Power Applications: A Second Look. I E E E Transactions on Industrial Electronics, 65(12), 9795-9800. [8331945]. https://doi.org/10.1109/TIE.2018.2823668

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2823668, IEEE Transactions on Industrial Electronics IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Steady-State Linear Kalman Filter-Based PLLs for Power Applications: A Second Look Saeed Golestan, Senior Member, IEEE, Josep M. Guerrero, Fellow, IEEE, and Juan. C. Vasquez, Senior Member, IEEE

Abstract—In three-phase power and energy applications, the synchronous reference frame phase-locked loop (SRFPLL) is a popular tool for the synchronization purposes. The SRF-PLL can be easily and effectively customized for different scenarios by changing its loop filter. Recently, some supposedly different PLLs using the steady-state linear Kalman filter (SSLKF) have been developed. The main aim of this letter is to analyze these PLLs. It is demonstrated that they are actually equivalent to some well-known SRFPLL structures and, therefore, provide no advantage compared to them.

va



v

dq

vd

ki s

vb vc

abc

v 

vq

va



v

dq

vd

n ki s

vb vc

abc v 

vq

Manuscript received October 3, 2017; revised January 24, 2018 and February 27, 2018; accepted March 19, 2018. Authors are with the Department of Energy Technology, Aalborg University, Aalborg DK-9220, Denmark (e-mail: [email protected]; [email protected]; [email protected]).



g

g 1 s sin cos



kp

I. I NTRODUCTION

T

s sin cos

(a)

Index Terms—Fixed gain filter, Kalman filter, phaselocked loop (PLL), synchronization, synchronous reference frame PLL (SRF-PLL), three-phase systems.

HE phase-locked loop (PLL) is regarded as one of the most popular tools for the grid synchronization of power electronics converters and extracting the grid voltage parameters in energy and power applications [1]–[3]. Recently, there have been intensive research efforts towards developing efficient PLLs. In three-phase systems, which this letter focuses on, the majority of these efforts are based on a standard structure, known as the synchronous reference frame PLL (SRF-PLL) [1]. The conventional SRF-PLL structure can be observed in Fig. 1(a). In this PLL, the phase error information is generated by transferring the three-phase grid voltage signals into the synchronous reference frame. The loop filter [a proportional-integral (PI) regulator] is responsible for regulating the phase error signal vq to zero, and its output signal is considered as an estimation of the grid voltage frequency. The conventional SRF-PLL has some drawbacks. The first problem is that the frequency estimated by the SRF-PLL undergoes an abrupt change when a phase jump happens [4]. This phenomenon is because of the coupling between frequency and phase variables. Notice that these parameters are estimated by a single loop in the conventional SRF-PLL [4]. Inspired by the enhanced PLL (EPLL) structure [3], [4], which has been developed based on an optimization procedure, this problem may be alleviated by tapping the frequency from

n ˆ g 1 



kp

g

(b) va



v

dq

vd



ki

vb vc

ka s

abc v 

vq

1 s

n 



kp

ˆ g 1 s sin cos

g

(c) va



v

dq

vd

abc v 

vq

n 

ki

vb vc

ka s 1 s



g 

kp

1 s sin cos

g

(d) Fig. 1. Block diagram of (a) conventional SRF-PLL, (b) enhanced SRFPLL (ESRF-PLL), (c) type-3 SRF-PLL, and (d) enhanced type-3 SRFPLL (ET3-SRF-PLL). va , vb , and vc denote the three-phase input signals of the PLLs, vα and vβ are the grid voltage signals in the stationary (αβ) frame, and vd and vq are the grid voltage signals in the synchronous (dq) frame. kp , ki , and ka are the loop filter parameters. ωn is the nominal value of the grid frequency. θ˜g is the estimated phase angle. ω ˆ g and ω ˜g both denote the estimated frequency.

the PI integrator output. Fig. 1(b), which is referred to as the enhanced SRF-PLL (ESRF-PLL), illustrates this idea. Another drawback of the conventional SRF-PLL is that it cannot follow frequency ramps with a zero phase error because

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it is a type-2 control system [5]. To deal with this problem, a type-3 SRF-PLL like that shown in Fig. 1(c) may be employed [6], [7]. The loop filter transfer function in this PLL is as kp + ki /s + ka /s2 , where kp , ki , and ka are its control parameters. The type-3 SRF-PLL, similar to the conventional SRF-PLL, suffers from a large transient in the estimated frequency when a phase angle jump happens. Therefore, it can be alleviated in a similar manner as the ESRF-PLL [see Fig. 1(d)]. This structure is referred to as the enhanced type-3 SRF-PLL (ET3SRF-PLL). Recently, some synchronization techniques for employing in power and energy applications have been designed which apparently have different structures compared to the conventional SRF-PLL and its variants. The general structure of these techniques, which are often referred to as the steady-state linear Kalman filter-based PLLs (SSLKF-PLLs)1 [8]–[10] and sometimes the fixed gain filter [11], can be observed in Fig. 2. As shown, the prediction and correction stages are two main parts of these techniques. The main aim of this letter is analysing these so-called new synchronization methods [8]–[11]. It is demonstrated here that they are equivalent with some well-known SRF-PLLs. This equivalence means that these synchronization techniques offer no advantage compared to the well-known SRF-PLLs. II. A NALYSIS

OF

SSLKF-PLL S

A. SSLKF-PLL Based on a Two-State Prediction Model Fig. 2, as mentioned before, illustrates the general structure of an SSLKF-PLL. In developing a two-state version of this PLL, it is assumed in [8] that the frequency of the PLL input signal does not experience large variations. Based on this assumption, the following two-state prediction model is considered [8] x(n) = Ax(n − 1) y(n) = Cx(n)       1 Ts T x = θg ωg ; A = ;C = 1 0 (1) 0 1 in which n denotes the current sample, θg and ωg are the grid voltage angle and angular frequency, respectively, and Ts is the sampling time. Throughout this letter, Ts = 0.0001 s (which corresponds to a sampling frequency equal to 10 kHz) is considered. Based on the model described in (1), the following steps are conducted by the prediction/correction filter to accurately estimate the state variables [8]: 1) Predicting the states at the next sampling time x ˜(n) = Aˆ x(n − 1).



v

dq

(3)

1 Strictly speaking, the SSLKF-PLL may not be regarded as a Kalman filter because, as shown in Fig. 2, its correction vector is fixed. Notice that implementing a Kalman filter involves adjusting its gains according to the Kalman filter theory in each sampling period.

vd

vb vc

abc

v 

vq

x(n) Correction xˆ( n )  x ( n ) vq ( n )

z 1

Prediction x(n) x(n)  Axˆ (n  1) sin  (n) cos g

Fig. 2. General structure of the SSLKF-PLL (also known as the fixed gain filter).

  where κT = κ1 κ2 is referred to as the correction vector, and θe (n) = θg (n) − C x ˜(n) = θg (n) − θ˜g (n). Based on (1)-(3), the PLL discrete-time implementation can be derived as shown in Fig. 3(a). This PLL is briefly called the SSLKF-PLL2 as it is based on a two-state prediction model. Notice that the signal vq (n) = sin(θg (n) − θ˜g (n)) ≈ θg (n) − θ˜g (n) = θe (n) contains the phase error information and is used for the correction stage. A hidden assumption here is considering the grid voltage amplitude equal to 1 p.u. By applying the block diagram algebra to the correction and prediction stages of Fig. 3(a), an alternative representation of the SSLKF-PLL2 can be achieved as shown in Fig. 3(b). Ts Ts z Notice that, in this structure, z−1 and z−1 describe two integrators discretized using backward and forward Euler methods, respectively. Considering this fact, the s-domain equivalent of the SSLKF-PLL2 can be obtained as illustrated in Fig. 3(c). This structure is the same as the ESRF-PLL [see Fig. 1(b)] if κ01 = κ1 /Ts = kp and κ02 = κ2 /Ts = ki . Therefore, it can be concluded that the SSLKF-PLL2 and the ESRF-PLL are equivalent systems. B. SSLKF-PLL Based on a Three-State Prediction Model In designing this PLL, it is assumed that large frequency ramping changes during normal operating conditions are likely. Based on this assumption, the following three-state prediction model is considered [9], [10] x(n) = Ax(n − 1) y(n) = Cx(n) 

xT = C=





θg

ωg

1 0 0

ag



1 Ts ;A =  0 1 0 0



 Ts2 /2 Ts  1 (4)

where ag = dωg /dt. Using this model, the state prediction/correction procedure can be carried out as follows x ˜(n) = Aˆ x(n − 1).

(2)

2) Correcting the predicted states using the phase error information x ˆ(n) = x ˜(n) + κθe (n)

va

(5)

x ˆ(n) = x ˜(n) + κθe (n) (6)  where κT = κ1 κ2 κ3 . Based on (4)-(6), the PLL structure shown in Fig. 4(a) can be derived. This PLL is named the SSLKF-PLL3 as it is based on a three-state prediction model. Using the block diagram algebra, the SSLKF-PLL3 can Ts z be rearranged as shown in Fig. 4(b). Considering that z−1 

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Correction va



v

dq

vd

ˆ (n) 1 ˆ g(n 1)  g z   (n) g

2

vb vc

abc

v  vq ( n )

g ( n ) Ts

va

ˆ (n) 1 ˆg(n 1)    g z

1

Correction Prediction aˆ g ( n ) 1 aˆg(n 1)  3 Ts  Ts /2 z ag(n)

Prediction

 g (n)



v

dq

vd

2

ˆ (n) 1 ˆ g(n 1)  g z

vc

g ( n )

Ts

vb

sin cos



v abc   vq ( n )

1



ˆg (n)

z

1

ˆg(n 1)  



sin cos

(a) va



v

dq

vd

vb vc

v abc   vq ( n )

(a)

Ts z z 1

 2

g ( n )

z 1 

1

Ts z 1

va

 g (n)



v

dq

 3

vd

vc

abc

Ts z z 1

v  vq ( n )

Ts /2 

 2

vb

sin cos

Ts z z 1

z 1

g ( n ) 



1

Ts z 1



v

dq

vd

(b)

 2

vb vc

v abc  

vq

1

g

1 s 

1 s

va

g



v

dq

vd

vc

abc

v 

 3  2

vb

sin cos

vq

1 s

Ts /2 

 

1 s

g

sin cos

Fig. 3. (a) SSLKF-PLL based on a two-state prediction model. This PLL is briefly referred to as the SSLKF-PLL2. (b) An alternative representation of the SSLKF-PLL2, which may be obtained by applying the block diagram algebra to Fig. 3(a). (c) The s-domain equivalent of the SSLKFPLL2. κ01 = κ1 /Ts and κ02 = κ2 /Ts . Ts are both discrete integrators, the s-domain equivalent and z−1 of Fig. 4(b) can be obtained as depicted in Fig. 4(c). The highlighted (red-color) path in Fig. 4(c) has a very negligible influence on the SSLKF-PLL3 performance as it has a very small gain (i.e., half the sampling period). By neglecting it, we can observe that the SSLKF-PLL3 and the ET3-SRF-PLL [see Fig. 1(d)] are equivalent systems if κ01 = κ1 /Ts = kp , κ02 = κ2 /Ts = ki , and κ03 = κ3 /Ts = ka . It is worth mentioning here that researchers who are working in the communication field are well aware of the strong similarity of PLLs and Kalman filters. They have reported these similarities in some research and tutorial articles [12]– [14].

III. T UNING A. SSLKF-PLL2 Using Fig. 3(c), the s-domain small-signal model of the SSLKF-PLL2 can be derived as shown in Fig. 5(a). Notice that, as mentioned before, the grid voltage amplitude is assumed to be 1 p.u. Based on this model, the closed-loop transfer function relating ωg to ω ˜ g can be derived as κ02 ωg (s). s2 + κ01 s + κ02

g

1 s 

1

(c)

ω ˜ g (s) =

 g (n)

sin cos

(b) va

 g (n)

(7)

By defining κ01 = κ1 /Ts = 2ζωn0 and κ02 = κ2 /Ts = (ωn0 )2 and selecting the natural frequency ωn0 and the damping factor

(c) Fig. 4. a) SSLKF-PLL based on a three-state prediction model. This structure is briefly called the SSLKF-PLL3. (b) An alternative representation of the SSLKF-PLL3, which is achieved by applying the block diagram algebra to Fig. 4(a). (c) The s-domain equivalent of the SSLKFPLL3. κ01 = κ1 /Ts , κ02 = κ2 /Ts , and κ03 = κ3 /Ts .

ζ according to the preferred (required) dynamic behavior, the SSLKF-PLL2 control parameters are chosen. Notice that the natural frequency is the most influential factor in determining the PLL bandwidth and, hence, its noise immunity and transient response speed, while ζ is the major factor in determining the damping of the dynamic response and, √consequently, the PLL phase margin (PM). Here, ζ = 1/ 2 (which in the literature is regarded as an optimum damping factor for second-order systems) and ωn0 = 125 rad/s are selected. These values correspond to κ1 = 0.01768 and κ2 = 1.5625.

B. SSLKF-PLL3 Using Fig. 4(c), the s-domain small-signal model of the SSLKF-PLL3 can be derived as shown in Fig. 5(b). For the sake of simplicity in the tuning procedure, we have neglected the highlighted (red color) path in Fig. 4(c). As mentioned before, it has a very negligible influence on the SSLKF-PLL3 performance. Using Fig. 5(b), the following open-loop transfer function can be obtained ω ˜ g (s) κ0 s + κ03 Gol (s) = = 22 . (8) ωg (s) − ω ˜ g (s) s (s + κ01 )

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2018.2823668, IEEE Transactions on Industrial Electronics IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

 2 g

Grid voltage (p.u.)

s

s

1





1 s



g

(a)

g 1  g s







1 g s 

1

0 -0.5 -1 0

 3 s

2

0.5

1 s

g

(b)

Estimated frequency (Hz)

g 1  g

1

0.02

0.04

0.06

0.08

0.1

Time (s) 75 70 65 60 55 50 45 0

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

0.02

0.04

0.06

0.08

0.1

Time (s)

TABLE I C ONTROL PARAMETERS

80 Phase error (deg)

Fig. 5. s-domain small-signal model of (a) the SSLKF-PLL2 and (b) the SSLKF-PLL3.

Parameters

In (9), ωc denotes the gain crossover frequency and determines the speed of dynamic response and the level of noise immunity, and b is a factor that specifies √ the PM as P M = tan−1 [(b2 − 1)/(2b)]. Here, b = 2 + 1 (which corresponds to P M = 45◦ ) and ωc = 125 rad/s are chosen. These values correspond to κ1 = 0.03018, κ2 = 3.7722, and κ3 = 195.3125. IV. P ERFORMANCE C OMPARISON To support the theoretical findings of this letter (i.e., the equivalence of the SSLKF-PLL2 [Fig. 3(a)] and ESRF-PLL [Fig. 1(b)], and the equivalence of the SSLKF-PLL3 [Fig. 4(a)] and ET3-SRF-PLL [Fig. 1(d)]), some numerical and experimental results are presented. The numerical results are obtained using Matlab/Simulink and the experimental ones are provided using a dSPACE platform. In obtaining the experimental results, the three-phase input signals of the PLLs are generated by the dSPACE platform. The control parameters of all PLLs can be found in Table I. It is worth mentioning here that the backward and forward Euler methods are used

20 0 -20 0.02

0.04

0.06

0.08

0.1

Time (s) (a) 1

Grid voltage (p.u.)

0.75 0.5 0.25 0 -0.25 -0.5 10 ms

-0.75

80 Estimated frequency (Hz)

Because this open-loop transfer function has two poles at the origin and a pole-zero pair with non-zero values, the symmetrical optimum method sounds to be the best option for selecting its control parameters [15], [16]. Applying this approach, which sets the gain crossover frequency at the geometric mean of the pole-zero pair to maximize the PM, yields κ01 = κ1 /Ts = bωc κ02 = κ2 /Ts = bωc2 (9) κ03 = κ3 /Ts = ωc3 .

40

0

κ1 = 0.01768, κ2 = 1.5625, kp =176.8, ki = 15625 κ1 = 0.03018, κ2 = 3.7722, κ3 = 195.3125 kp =301.8, ki = 37722, ka = 1953125

75 70 65

60

SSLKF-PLL3 SSLKF-PLL2

55 50

ET3-SRF-PLL

10 ms

45

ESRF-PLL

80

60 Phase error (deg)

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

60

40 20

SSLKF-PLL3 SSLKF-PLL2

0 -20

-40

ET3-SRF-PLL ESRF-PLL

-60

10 ms

(b)

Fig. 6. (a) Simulation results and (b) experimental results of Test 1.

for the discretization of the loop filter and voltage-controlled oscillator of the SRF-PLLs, respectively.

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Grid voltage (p.u.)

0.5 0 -0.5 -1 0

0.02

0.04

0.06

0.08

Estimated frequency (Hz)

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL 0.02

0.04

0.06

0.08

0.1

3 0 -3 0

0.02

0.04

0.06

0.08

0.1

Phase error (deg)

Phase error (deg)

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

6

0 -0.5 -1 0

Time (s) 9

0.5

0.1

Time (s) 57 56 55 54 53 52 51 50 49 0

1

Estimated frequency (Hz)

Grid voltage (p.u.)

1

0.04

0.08 Time (s)

0.12

0.16

54 53 52

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

51 50 49 0

1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 0

0.04

0.08 Time (s)

0.12

0.16

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

0.04

0.08 Time (s)

0.12

0.16

Time (s)

Fig. 9. Simulation results of Test 4.

Grid voltage (p.u.)

Fig. 7. Simulation results of Test 2. 1 0.5 0 -0.5

Estimated frequency (Hz)

-1 0

0.02

0.04

0.06

0.08

0.1

Time (s) 51.5 51 50.5 50 49.5 49 48.5 0

SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

0.02

0.04

0.06

0.08

0.1

Time (s) Phase error (deg)

4 SSLKF-PLL2 ESRF-PLL SSLKF-PLL3 ET3-SRF-PLL

2 0 -2 -4 0

0.02

0.04

0.06

0.08

0.1

Time (s)

Fig. 8. Simulation results of Test 3.

Four tests are performed. The description of these tests is as follows. Test 1: A 80◦ phase angle jump. Test 2: A +5 Hz frequency jump under a harmonically distorted and imbalanced grid condition.

Test 3: Presence of 0.1 p.u. dc component in one phase of the grid voltage three-phase signal. Test 4: A +40 Hz/s ramping change in the grid voltage frequency for a duration of 0.075 s. Fig. 6 shows the simulation and experimental results of Test 1. Table II summarizes the details of the obtained results. As expected, the SSLKF-PLLs and their corresponding SRFPLLs demonstrate well-matched results. To save the space, the experimental results are not shown for the rest of the tests. Figs. 7, 8, and 9 demonstrate the simulation results of Tests 2, 3, and 4, respectively. The details can be found in Table II. In all these tests, again, it is observed that the SSLKF-PLLs and their corresponding SRF-PLLs demonstrate well-matched results. V. C ONCLUSION In this letter, an analysis of two SSLKF-PLLs, which have been recently designed and proposed for the synchronization in power and energy applications, was conducted. It was shown that these SSLKF-PLLs are mathematically equivalent to two well-known SRF-PLLs, which have a rather long history of use in power and energy applications. To support this theoretical finding, some numerical and experimental tests were conducted. The obtained results were confirmed that the SSLKF-PLLs and their corresponding SRF-PLLs are equivalent systems. It means that the SSLKF-PLLs have no advantage/disadvantage compared to their corresponding SRFPLLs. R EFERENCES [1] S. Golestan, J. M. Guerrero, and J. C. Vasquez, “Three-phase PLLs: A review of recent advances,” IEEE Trans. Power Electron., vol. 32, no. 3, pp. 1894–1907, Mar. 2017.

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S UMMARY

OF

TABLE II R ESULTS . B/A D ENOTES B EFORE /A FTER

THE

F REQUENCY J UMP.

SSLKF-PLL2/ESRF-PLL

SSLKF-PLL3/ET3-SRF-PLL

40 ms (2 cycles) 16.6◦ (20.7%) 12.5 Hz

52 ms (2.6 cycles) 20.5◦ (25.6%) 22.3 Hz

1.92◦ /1.75◦ 0.46 Hz/0.42 Hz

3.2◦ /2.93◦ 1.09 Hz/1 Hz

4.46◦ 1.05 Hz

6.93◦ 2.39 Hz

0.92◦

0◦

Test 1 2% settling time Phase overshoot Peak frequency deviation Test 2 Peak-to-peak phase error (B/A) Peak-to-peak frequency error (B/A) Test 3 Peak-to-peak phase error Peak-to-peak frequency error Test 4 Steady-phase phase error during frequency ramp

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