A Novel Dynamic Threshold Operation

A Novel Dynamic Threshold Operation Using the Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime Abhisek Dixit and V. Ramgopa...

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A Novel Dynamic Threshold Operation Using the Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime Abhisek Dixit and V. Ramgopal Rao* Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai- 400 076 INDIA * [email protected]

Abstract With CMOS scaling into the Sub-100nm regime, the supply and the threshold voltages need to be scaled proportionately. This necessitates addressing of low power CMOS device design issues. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to addressing the problems associated with device scaling for low power CMOS. This work focuses on the device optimisation for such low power ULSI circuits using a novel Electrically induced junction (EJ)-MOSFET as a DTMOS. Such an implementation can be used without the additional substrate loading effects and the supply voltage limitations, commonly associated with conventional DTMOS operation. Our detailed dc as well as transient simulations bring out the advantages of this novel structure.

1.

Introduction

The dynamic threshold MOSFET (DTMOS) operation has attracted lot of interest in CMOS community in the last few years [1]. The need for such a device arises for low power, high performance applications. There are many ways a DTMOS can be implemented in Very Large Scale Integrated (VLSI) circuits. One and foremost of those is by tying substrate of the transistor to its gate. As the substrate bias increases (VSUB), along with the gate bias (VGS), bulk charge in silicon is compensated. This reduction in bulk charge lowers VT of the device and consequently leads to a higher drive current (ION) due to increased available gate overdrive VGT (=VGS−VT). However, such an implementation cannot be used for supply voltages above the cut-in voltages of the S/D junctions. More importantly, the bulk capacitance of transistor adds to

total parasitic capacitance at the input (CIN), which must be charged by the input signal. Thus, this simple DTMOS implementation achieves higher ION while increasing the CIN, with the overall result that there is degradation in the circuit speed. In this work, we propose a novel implementation of DTMOS using Electrically Induced Junction (EJ) MOSFET. The performance of both the implementations has been evaluated using dc as well as transient simulations.

2.

EJ-MOSFET

An EJ-MOSFET device has been shown to improve the device performance by a few researchers [2]. An alternative and better scheme to implement the EJMOSFET has been recently reported [3]. The latter achieves superior device characteristics due to replacement of its shallow n+ extensions with shallow p− extensions. In such a device, as shown in Fig. 1, the effective channel length (LCH) is lower, compared to a conventional MOSFET, as longer and inverted p− regions act as shallow extensions in the presence of VGS, i.e. LON
3.

Simulation

ISETCAD [4] process simulator DIOS, device simulator DESSIS, and mesh generator MDRAW have been used for all the energy balance and mixed-mode simulations reported in this work. Here we compare the performance of three devices, namely, the conventional

LCH LG

(a)

N+ P−

LON LOFF

(b)

Figure 1. Device structures: (a) conventional device (b) EJ-MOSFET

4.

Results and discussion

The p− regions have first been superimposed by mesh-generation tool on a conventional device structure, simulated using process simulation. In order to optimise the EJ-MOSFET, ION and IOFF have been plotted as a function of the length of p− region with doping concentration as a parameter, shown in figures 2 and 3.

10

ION (mA /µm)

-3

15

-3

17

-3

10 (cm ) 10 (cm )

0.6

15

-3

17

-3

10 (cm ) 0

10

10

-1

10

-2

35

40 45 50 − P -region Length (nm)

Figure 3. IOFF as a function of p− region length To optimise the device performance, length and doping concentration of p− regions is chosen to be 45nm and 1015 (cm-3) respectively. Further, ID−VGS characteristics of the three devices have been compared in Fig. 4. Here, VDS has been kept at a low value (=0.05V) and VGS is ramped from 0 to 1.0V for conventional and EJ-MOSFET devices. VGS for DTMOS device has been ramped only up to 0.8V in order to prevent turn-on of the substrate-source/drain (S/D) diodes.

120 100 ID (µA /µm)

18

-3

10 (cm )

80

0.7

18

10 (cm ) 1

IOFF (nA /µm)

device, a DTMOS device that has its substrate tied to gate, and EJ-MOSFET that has been simulated with a few modifications in conventional CMOS process flow. The conventional device has a gate length of 120nm and all other technology parameters conform to SIA projections [5]-[6] for this technology node.

Conventional DTMOS EJ-MOSFET

1E-4 1E-6 1E-8 1E-10 0.0

0.5

1.0

60 40 20

10 (cm ) 0 0.0 0.2 0.4 0.6 0.8 1.0 VGS (V)

0.5 0.4 0.3

Figure 4. ID−VGS, inset shows the semi-log plot 35

40 45 50 − P -region Length (nm)

Figure 2. ION as a function of p− region length As can be seen from Fig. 2, ION increases with length of the p− regions. This is because LON decreases for VG>VT as length of p− regions increases. ION also increases with decrease in the doping of p− regions as lower the doping, higher will be the inversion layer charge in the p− regions, decreasing the series resistance. Fig.3 shows that longer p− regions result in higher IOFF. This is because of a reduction in LON with increasing p- length. Higher doping in the p- regions lowers IOFF, at the same time reducing ION.

It is seen from Fig. 4 that DTMOS achieves higher drive currents compared to the EJ-MOSFET and conventional devices. The improvement of EJ-MOSFET over conventional device can also be clearly seen in this figure. Inset in Fig. 4 shows the same ID−VGS plot on the semi-log scale, which shows that sub-threshold currents are nearly identical for all three devices. Figure 5 shows ID-VDS characteristics for three devices at VGS values of 0.3V, 0.6V, and 0.8V. In this simulation, VDS has been ramped from 0 to 1.0V. As expected from Fig. 4, ID in Fig. 5 is highest for DTMOS device and lowest for conventional device, for all the three VGS values. Whereas, a close examination of Fig. 5 reveals that EJMOSFET also shows improved saturation behaviour

which could be beneficial for analog applications. The improvement is expected because of the induced shallow inversion layer acting as source-drain extensions.

0.5

Conventional DTMOS VGS=0.8V EJ-MOSFET

ID (mA /µm)

0.4

1.5µ µ/0.12µ µ +

V



I

C

+ −

1µ µ/0.12µ µ

0.3 VGS=0.6V

0.2 0.1

VGS=0.3V

0.0 0.0 0.2 0.4 0.6 0.8 1.0 VDS (V)

Figure 5. ID−VDS characteristics

1.0

Conventional DTMOS EJ-MOSFET

ION (mA /µm)

0.8 0.6

Figure 7. Circuit diagram for capacitance extraction In Fig. 7, a voltage pulse (0-VDD) drives input of the inverter. The unity gain current-controlled-currentsource (CCCS) “I” is controlled by current flowing through the voltage source “V”. This current integrated over the rise time of input pulse using a 100fF capacitor “C”, gives CIN of the inverter. CIN values extracted by this method come out to be 5fF, 7.33fF and 4.9fF for conventional, DTMOS (gate-tied-to-body) and EJMOSFET devices, respectively. The higher CIN value for DTMOS inverter, as compared to a conventional inverter, is due to additional substrate capacitance that comes in parallel with CIN of a conventional inverter.

0.4 0.2

0

2

1.5µ µ/0.12µ µ

4 6 8 10 12 IOFF (nA /µm)

Figure 6. ION at various IOFF values In order to estimate the maximum ION that can be achieved for a given IOFF value, the three structures are compared for their drive currents at identical IOFF values in Fig. 6. As can be seen, EJ-MOSFET scores over the conventional MOSFET in terms of better ION-IOFF performance. This suggests that the on current can be optimised in the case of EJ-MOSFET by a proper design of p- length and doping concentrations. In order to evaluate the transient performance of these devices, the DESSIS-SPICE interface of ISETCAD [4] has been used for mixed-mode simulations. Firstly, p-channel MOSFETs with identical VT values have been simulated for the three structures. Then circuit schematic shown in Fig. 7 is used to extract the input capacitance of the three CMOS inverters. The n-channel MOSFETs in the inverter have a width (WN) to length ratio (WN/L) of 10, whereas width of pchannel transistors (WP) has been adjusted to make the rise and fall delay values equal (WP/WN=1.5, for all three devices).

V

1µ µ/0.12µ µ

+ −

CIN

Figure 8. Circuit diagram for delay extraction Figure 8 shows the CMOS inverter used to extract propagation delay for the three cases. This circuit has been designed to operate at an electrical effort (H=COUT/CIN) equal to 1, i.e. the inverter drives a capacitive load equal to its own CIN value. Further, Fig. 9 shows the propagation delay (τ) as a function of supply voltage (VDD). As can be seen from Fig. 9, higher CIN value of DTMOS inverter degrades its transient performance offsetting any improvement that is expected due to improved transistor drive current. On the other hand, EJ-MOSFET inverter achieves lowest delay values amongst the three inverters at all VDD values. Also, as can be seen from Fig. 9, the delay advantage with EJ-MOSFET inverter improves with supply voltage scaling.

This suggests that EJ-MOSFET can play a vital role in optimising performance of deep sub-micrometer CMOS for low power applications. Propagation Delay, τ (ps)

100 80

Conventional DTMOS EJ-MOSFET

60 40 20 0.4

0.6 0.8 1.0 Supply Voltage, VDD (V)

Figure 9. Propagation delay as a function of VDD

5.

Conclusions

Both dc and transient performance of EJ-MOSFET device has been compared with conventional and DTMOS devices. The EJ-MOSFET device shows moderate improvement in the dc characteristics (as compared to DTMOS) over the conventional MOSFET structures, and superior transient characteristics amongst all the three devices. It is also clear from these simulations that with proper optimisation of EJMOSFET parameters (p- doping and length), it is possible to modulate its threshold voltage without the associated substrate loading effects.

12. References [1] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-low Voltage VLSI”, IEEE Trans. Electron Devices, vol. 44 (3), March 1997, pp. 414-421. [2] H. Noda, F. Murai, and S. Kimura, “Short Channel Characteristics of Si MOSFET With Extremely Shallow Source and Drain Regions Formed by Inversion Layers”, IEEE Trans. on Electron Devices, 41 (10), 1994, pp 1831. [3] A. Dixit, R. O. Dusane, and V. Ramgopal Rao, “Electrically Induced Junction MOSFET for High Performance Sub-50nm CMOS Technology”, The Proceedings of The Materials Research Society (MRS)”, San Francisco USA, April 2002. [4] ISE TCAD User’s Manual-Release 6(1, 3, 4, 5), Integrated Systems Engineering AG, Technoparkstrasse 1, CH-8005 Zurich / Switzerland. [5] Y. A. El-Mansy, “VLSI Symposium and Silicon Technology: a twenty year perspective”, Symposium on VLSI Technology Digest of Technical Papers, 2000, pp 2.

[6] S. Song, J. H. Yi, W. S. Kim, J. S. Lee, K. Fujihara, H. K. Kang, J. T. Moon, and M. Y. Lee, “CMOS device scaling beyond 100nm”, The International Electron Devices Meeting IEDM 00, 2000, pp 235.